package_counter.vhd

来自「这是关于VHDL模块的源代码」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package package_counter is
    component counter_10
         port(clk:in std_logic;
              clr:in std_logic;
              en: in std_logic;
              counter_out: out std_logic_vector(3 downto 0);
              carry_out: out std_logic);
    end component;

    component reg_32bit
         port(load:in std_logic;
              din:in std_logic_vector(31 downto 0);
              dout:out std_logic_vector(31 downto 0));
    end component;

    component counter_ctrl
         port(clk:in std_logic;
              counter_en:out std_logic;
              clr_counter:out std_logic;
              load:out std_logic);
    end component;
end package_counter;