frequency_counter_2.map.summary

来自「这是关于VHDL模块的源代码」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Tue Oct 11 22:24:59 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : frequency_counter_2
Top-level Entity Name : frequency_counter_2
Family : Stratix
Met timing requirements : N/A
Total logic elements : 72
Total pins : 34
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0