counter_ctrl.vhd

来自「这是关于VHDL模块的源代码」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_ctrl is
    port(clk:in std_logic;
         counter_en:out std_logic;
         clr_counter:out std_logic;
         load:out std_logic);
end counter_ctrl;

architecture behave of counter_ctrl is
   signal div_2_clk:std_logic:='1';
begin
    process(clk)
    begin
         if clk'event and clk='1' then
              div_2_clk<=not div_2_clk;
         end if;
    end process;

    process(clk,div_2_clk)
    begin
        if  (clk='0' and div_2_clk='0')  then
             clr_counter<='1';
        else 
             clr_counter<='0';
        end if;
    end process;
    
    load<=not div_2_clk;
    counter_en<=div_2_clk;
end behave;