frequency_counter_2.hier_info

这是关于VHDL模块的源代码

|frequency_counter_2
fsin => counter_10:u0_counter_10.clk
clk => counter_ctrl:u_counter_ctrl.clk
dout[0] <= reg_32bit:u_reg_32bit.dout[0]
dout[1] <= reg_32bit:u_reg_32bit.dout[1]
dout[2] <= reg_32bit:u_reg_32bit.dout[2]
dout[3] <= reg_32bit:u_reg_32bit.dout[3]
dout[4] <= reg_32bit:u_reg_32bit.dout[4]
dout[5] <= reg_32bit:u_reg_32bit.dout[5]
dout[6] <= reg_32bit:u_reg_32bit.dout[6]
dout[7] <= reg_32bit:u_reg_32bit.dout[7]
dout[8] <= reg_32bit:u_reg_32bit.dout[8]
dout[9] <= reg_32bit:u_reg_32bit.dout[9]
dout[10] <= reg_32bit:u_reg_32bit.dout[10]
dout[11] <= reg_32bit:u_reg_32bit.dout[11]
dout[12] <= reg_32bit:u_reg_32bit.dout[12]
dout[13] <= reg_32bit:u_reg_32bit.dout[13]
dout[14] <= reg_32bit:u_reg_32bit.dout[14]
dout[15] <= reg_32bit:u_reg_32bit.dout[15]
dout[16] <= reg_32bit:u_reg_32bit.dout[16]
dout[17] <= reg_32bit:u_reg_32bit.dout[17]
dout[18] <= reg_32bit:u_reg_32bit.dout[18]
dout[19] <= reg_32bit:u_reg_32bit.dout[19]
dout[20] <= reg_32bit:u_reg_32bit.dout[20]
dout[21] <= reg_32bit:u_reg_32bit.dout[21]
dout[22] <= reg_32bit:u_reg_32bit.dout[22]
dout[23] <= reg_32bit:u_reg_32bit.dout[23]
dout[24] <= reg_32bit:u_reg_32bit.dout[24]
dout[25] <= reg_32bit:u_reg_32bit.dout[25]
dout[26] <= reg_32bit:u_reg_32bit.dout[26]
dout[27] <= reg_32bit:u_reg_32bit.dout[27]
dout[28] <= reg_32bit:u_reg_32bit.dout[28]
dout[29] <= reg_32bit:u_reg_32bit.dout[29]
dout[30] <= reg_32bit:u_reg_32bit.dout[30]
dout[31] <= reg_32bit:u_reg_32bit.dout[31]


|frequency_counter_2|counter_ctrl:u_counter_ctrl
clk => div_2_clk.CLK
clk => process1~0.IN1
counter_en <= div_2_clk.DB_MAX_OUTPUT_PORT_TYPE
clr_counter <= process1~0.DB_MAX_OUTPUT_PORT_TYPE
load <= div_2_clk.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|reg_32bit:u_reg_32bit
load => dout[30]~reg0.CLK
load => dout[29]~reg0.CLK
load => dout[28]~reg0.CLK
load => dout[27]~reg0.CLK
load => dout[26]~reg0.CLK
load => dout[25]~reg0.CLK
load => dout[24]~reg0.CLK
load => dout[23]~reg0.CLK
load => dout[22]~reg0.CLK
load => dout[21]~reg0.CLK
load => dout[20]~reg0.CLK
load => dout[19]~reg0.CLK
load => dout[18]~reg0.CLK
load => dout[17]~reg0.CLK
load => dout[16]~reg0.CLK
load => dout[15]~reg0.CLK
load => dout[14]~reg0.CLK
load => dout[13]~reg0.CLK
load => dout[12]~reg0.CLK
load => dout[11]~reg0.CLK
load => dout[10]~reg0.CLK
load => dout[9]~reg0.CLK
load => dout[8]~reg0.CLK
load => dout[7]~reg0.CLK
load => dout[6]~reg0.CLK
load => dout[5]~reg0.CLK
load => dout[4]~reg0.CLK
load => dout[3]~reg0.CLK
load => dout[2]~reg0.CLK
load => dout[1]~reg0.CLK
load => dout[0]~reg0.CLK
load => dout[31]~reg0.CLK
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
din[10] => dout[10]~reg0.DATAIN
din[11] => dout[11]~reg0.DATAIN
din[12] => dout[12]~reg0.DATAIN
din[13] => dout[13]~reg0.DATAIN
din[14] => dout[14]~reg0.DATAIN
din[15] => dout[15]~reg0.DATAIN
din[16] => dout[16]~reg0.DATAIN
din[17] => dout[17]~reg0.DATAIN
din[18] => dout[18]~reg0.DATAIN
din[19] => dout[19]~reg0.DATAIN
din[20] => dout[20]~reg0.DATAIN
din[21] => dout[21]~reg0.DATAIN
din[22] => dout[22]~reg0.DATAIN
din[23] => dout[23]~reg0.DATAIN
din[24] => dout[24]~reg0.DATAIN
din[25] => dout[25]~reg0.DATAIN
din[26] => dout[26]~reg0.DATAIN
din[27] => dout[27]~reg0.DATAIN
din[28] => dout[28]~reg0.DATAIN
din[29] => dout[29]~reg0.DATAIN
din[30] => dout[30]~reg0.DATAIN
din[31] => dout[31]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[16] <= dout[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[17] <= dout[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[18] <= dout[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[19] <= dout[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[20] <= dout[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[21] <= dout[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[22] <= dout[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[23] <= dout[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[24] <= dout[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[25] <= dout[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[26] <= dout[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[27] <= dout[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[28] <= dout[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[29] <= dout[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[30] <= dout[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[31] <= dout[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u0_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u1_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u2_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u3_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u4_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u5_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u6_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|frequency_counter_2|counter_10:u7_counter_10
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => counter[3].CLK
clr => counter[2].ACLR
clr => counter[1].ACLR
clr => counter[0].ACLR
clr => counter[3].ACLR
en => counter[2].ENA
en => counter[1].ENA
en => counter[0].ENA
en => counter[3].ENA
counter_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
carry_out <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE