counter_10.vhd

这是关于VHDL模块的源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_10 is 
   port(clk:in std_logic;
        clr:in std_logic;
        en: in std_logic;
        counter_out: out std_logic_vector(3 downto 0);
        carry_out: out std_logic);
end counter_10;

architecture behave of counter_10 is
   signal counter: std_logic_vector(3 downto 0);
begin
   process(clk,clr,en)
   begin
       if clr='1'      then
              counter<="0000";
       elsif clk'event and clk='1' then
             if en='1'  then
                   if counter<"1001"    then 
                         counter<=counter+1;
                   else 
                         counter<="0000";
                   end if;
             end if;
       end if;
   end process;

   process(counter)    
   begin
        if counter="1001"    then
              carry_out<='1';
        else 
              carry_out<='0';
        end if;
   end process;
   counter_out<=counter;
end behave;