frequency_counter_2.map.rpt

这是关于VHDL模块的源代码

+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                            ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                               ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------+
; frequency_counter_2.vhd          ; yes             ; User VHDL File  ; E:/quartus_project/frequency_counter_2(successful)/frequency_counter_2.vhd ;
; counter_10.vhd                   ; yes             ; User VHDL File  ; E:/quartus_project/frequency_counter_2(successful)/counter_10.vhd          ;
; reg_32bit.vhd                    ; yes             ; User VHDL File  ; E:/quartus_project/frequency_counter_2(successful)/reg_32bit.vhd           ;
; counter_ctrl.vhd                 ; yes             ; User VHDL File  ; E:/quartus_project/frequency_counter_2(successful)/counter_ctrl.vhd        ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------------+


+--------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                              ;
+---------------------------------+----------------------------------------+
; Resource                        ; Usage                                  ;
+---------------------------------+----------------------------------------+
; Total logic elements            ; 72                                     ;
; Total combinational functions   ; 39                                     ;
;     -- Total 4-input functions  ; 30                                     ;
;     -- Total 3-input functions  ; 8                                      ;
;     -- Total 2-input functions  ; 1                                      ;
;     -- Total 1-input functions  ; 0                                      ;
;     -- Total 0-input functions  ; 0                                      ;
; Combinational cells for routing ; 0                                      ;
; Total registers                 ; 65                                     ;
; I/O pins                        ; 34                                     ;
; Maximum fan-out node            ; counter_ctrl:u_counter_ctrl|counter_en ;
; Maximum fan-out                 ; 66                                     ;
; Total fan-out                   ; 340                                    ;
; Average fan-out                 ; 3.21                                   ;
+---------------------------------+----------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                           ;
+----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------+
; Compilation Hierarchy Node       ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                              ;
+----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------+
; |frequency_counter_2             ; 72 (0)      ; 65           ; 0           ; 0            ; 0       ; 0         ; 0         ; 34   ; 0            ; 7 (0)        ; 33 (0)            ; 32 (0)           ; 0 (0)           ; |frequency_counter_2                             ;
;    |counter_10:u0_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u0_counter_10    ;
;    |counter_10:u1_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u1_counter_10    ;
;    |counter_10:u2_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u2_counter_10    ;
;    |counter_10:u3_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u3_counter_10    ;
;    |counter_10:u4_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u4_counter_10    ;
;    |counter_10:u5_counter_10|    ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u5_counter_10    ;
;    |counter_10:u6_counter_10|    ; 5 (5)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u6_counter_10    ;
;    |counter_10:u7_counter_10|    ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |frequency_counter_2|counter_10:u7_counter_10    ;
;    |counter_ctrl:u_counter_ctrl| ; 2 (2)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |frequency_counter_2|counter_ctrl:u_counter_ctrl ;
;    |reg_32bit:u_reg_32bit|       ; 32 (32)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |frequency_counter_2|reg_32bit:u_reg_32bit       ;
+----------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 65    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 32    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/quartus_project/frequency_counter_2(successful)/frequency_counter_2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Oct 11 22:24:48 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off frequency_counter_2 -c frequency_counter_2
Info: Found 2 design units, including 1 entities, in source file frequency_counter_2.vhd
    Info: Found design unit 1: frequency_counter_2-frequency_counter_2
    Info: Found entity 1: frequency_counter_2
Info: Found 2 design units, including 1 entities, in source file counter_10.vhd
    Info: Found design unit 1: counter_10-behave
    Info: Found entity 1: counter_10
Info: Found 2 design units, including 1 entities, in source file reg_32bit.vhd
    Info: Found design unit 1: reg_32bit-behave
    Info: Found entity 1: reg_32bit
Info: Found 2 design units, including 1 entities, in source file counter_ctrl.vhd
    Info: Found design unit 1: counter_ctrl-behave
    Info: Found entity 1: counter_ctrl
Info: Found 1 design units, including 0 entities, in source file package_counter.vhd
    Info: Found design unit 1: package_counter
Info: Elaborating entity "frequency_counter_2" for the top level hierarchy
Info: Elaborating entity "counter_ctrl" for hierarchy "counter_ctrl:u_counter_ctrl"
Info: Elaborating entity "reg_32bit" for hierarchy "reg_32bit:u_reg_32bit"
Info: Elaborating entity "counter_10" for hierarchy "counter_10:u0_counter_10"
Info: Implemented 106 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 32 output pins
    Info: Implemented 72 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Oct 11 22:24:59 2005
    Info: Elapsed time: 00:00:12