dct8_medium.vhd

来自「算术处理器的VERILOG hdl的源代码」· VHDL 代码 · 共 2,683 行 · 第 1/5 页

END MACXe2 ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF MACXe2 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL Sout      : unsigned(11 DOWNTO 0);
SIGNAL aout      : unsigned(11 DOWNTO 0);
SIGNAL aout_1    : unsigned(12 DOWNTO 0);
SIGNAL aout_2    : unsigned(13 DOWNTO 0);
SIGNAL bin       : unsigned(13 DOWNTO 0);
SIGNAL coeff_out : unsigned(11 downto 0);
SIGNAL output    : unsigned(12 DOWNTO 0);
SIGNAL output_1  : unsigned(13 DOWNTO 0);

-- Component Declarations
COMPONENT ROMC_e2
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      compl      : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      coeff_out  : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add12signed
   PORT (
      a      : IN     unsigned (11 DOWNTO 0);
      b      : IN     unsigned (11 DOWNTO 0);
      output : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add14signed
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      bin    : IN     unsigned (13 DOWNTO 0);
      output : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT div2
   PORT (
      Sin  : IN     unsigned (12 downto 0);
      Sout : OUT    unsigned (11 downto 0)
   );
END COMPONENT;
COMPONENT reg12b
   PORT (
      ain    : IN     unsigned (11 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg13b
   PORT (
      ain    : IN     unsigned (12 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg14b
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;

-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROMC_e2 USE ENTITY work.ROMC_e2;
FOR ALL : add12signed USE ENTITY work.add12signed;
FOR ALL : add14signed USE ENTITY work.add14signed;
FOR ALL : div2 USE ENTITY work.div2;
FOR ALL : reg12b USE ENTITY work.reg12b;
FOR ALL : reg13b USE ENTITY work.reg13b;
FOR ALL : reg14b USE ENTITY work.reg14b;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
bin <= aout_1(12)&aout_1;


   -- Instance port mappings.
   I0 : ROMC_e2
      PORT MAP (
         addr2      => addr2,
         compl      => compl,
         enable_rom => enable_rom,
         coeff_out  => coeff_out
      );
   I3 : add12signed
      PORT MAP (
         a      => Sout,
         b      => aout,
         output => output
      );
   I6 : add14signed
      PORT MAP (
         ain    => aout_2,
         bin    => bin,
         output => output_1
      );
   I5 : div2
      PORT MAP (
         Sin  => aout_1,
         Sout => Sout
      );
   I2 : reg12b
      PORT MAP (

         ain    => coeff_out,
         clk    => clk,
         enable => enable,
         aout   => aout
      );
   I4 : reg13b
      PORT MAP (
         ain    => output,
         clk    => clk,
         enable => enable,
         aout   => aout_1
      );
   I7 : reg14b
      PORT MAP (
         ain    => output_1,
         clk    => clk_1,
         enable => enable_1,
         aout   => aout_2
      );
   I8 : reg14b
      PORT MAP (
         ain    => aout_2,
         clk    => clk_2,
         enable => enable_2,
         aout   => aout_3
      );

END struct;

--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY MACXe3 IS
   PORT( 
      addr2      : IN     unsigned (1 DOWNTO 0) ;
      clk        : IN     std_ulogic  ;
      clk_1      : IN     std_ulogic  ;
      clk_2      : IN     std_ulogic  ;
      compl      : IN     std_ulogic  ;
      enable     : IN     std_ulogic  ;
      enable_1   : IN     std_ulogic  ;
      enable_2   : IN     std_ulogic  ;
      enable_rom : IN     std_ulogic  ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );

-- Declarations

END MACXe3 ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF MACXe3 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL Sout      : unsigned(11 DOWNTO 0);
SIGNAL aout      : unsigned(11 DOWNTO 0);
SIGNAL aout_1    : unsigned(12 DOWNTO 0);
SIGNAL aout_2    : unsigned(13 DOWNTO 0);
SIGNAL bin       : unsigned(13 DOWNTO 0);
SIGNAL coeff_out : unsigned(11 downto 0);
SIGNAL output    : unsigned(12 DOWNTO 0);
SIGNAL output_1  : unsigned(13 DOWNTO 0);

-- Component Declarations
COMPONENT ROMC_e3
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      compl      : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      coeff_out  : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add12signed
   PORT (
      a      : IN     unsigned (11 DOWNTO 0);
      b      : IN     unsigned (11 DOWNTO 0);
      output : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add14signed
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      bin    : IN     unsigned (13 DOWNTO 0);
      output : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT div2
   PORT (
      Sin  : IN     unsigned (12 downto 0);
      Sout : OUT    unsigned (11 downto 0)
   );
END COMPONENT;
COMPONENT reg12b
   PORT (
      ain    : IN     unsigned (11 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg13b
   PORT (
      ain    : IN     unsigned (12 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg14b
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;

-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROMC_e3 USE ENTITY work.ROMC_e3;
FOR ALL : add12signed USE ENTITY work.add12signed;
FOR ALL : add14signed USE ENTITY work.add14signed;
FOR ALL : div2 USE ENTITY work.div2;
FOR ALL : reg12b USE ENTITY work.reg12b;
FOR ALL : reg13b USE ENTITY work.reg13b;
FOR ALL : reg14b USE ENTITY work.reg14b;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
bin <= aout_1(12)&aout_1;


   -- Instance port mappings.
   I0 : ROMC_e3
      PORT MAP (
         addr2      => addr2,
         compl      => compl,
         enable_rom => enable_rom,
         coeff_out  => coeff_out
      );
   I3 : add12signed
      PORT MAP (
         a      => Sout,
         b      => aout,
         output => output
      );
   I6 : add14signed
      PORT MAP (
         ain    => aout_2,
         bin    => bin,
         output => output_1
      );
   I5 : div2
      PORT MAP (
         Sin  => aout_1,
         Sout => Sout
      );
   I2 : reg12b
      PORT MAP (

         ain    => coeff_out,
         clk    => clk,
         enable => enable,
         aout   => aout
      );
   I4 : reg13b
      PORT MAP (
         ain    => output,
         clk    => clk,
         enable => enable,
         aout   => aout_1
      );
   I7 : reg14b
      PORT MAP (
         ain    => output_1,
         clk    => clk_1,
         enable => enable_1,
         aout   => aout_2
      );
   I8 : reg14b
      PORT MAP (
         ain    => aout_2,
         clk    => clk_2,
         enable => enable_2,
         aout   => aout_3
      );

END struct;

--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY DCT8_core IS
   PORT( 
      bit_in   : IN     std_ulogic  ;
      bit_in_2 : IN     std_logic  ;
      clk      : IN     std_ulogic  ;
      reset    : IN     std_ulogic  ;
      dbus00   : OUT    unsigned (13 DOWNTO 0) ;
      dbus01   : OUT    unsigned (13 DOWNTO 0) ;
      dbus02   : OUT    unsigned (13 DOWNTO 0) ;
      dbus03   : OUT    unsigned (13 DOWNTO 0) ;
      dbuse0   : OUT    unsigned (13 DOWNTO 0) ;
      dbuse1   : OUT    unsigned (13 DOWNTO 0) ;
      dbuse2   : OUT    unsigned (13 DOWNTO 0) ;
      dbuse3   : OUT    unsigned (13 DOWNTO 0) ;
      sig00    : OUT    std_ulogic  ;
      sig01    : OUT    std_ulogic  ;
      sig02    : OUT    std_ulogic  ;
      sig03    : OUT    std_ulogic 
   );

-- Declarations

END DCT8_core ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF DCT8_core IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL address          : unsigned(1 DOWNTO 0);
SIGNAL address_out      : unsigned(1 DOWNTO 0);
SIGNAL address_out_1    : unsigned(1 DOWNTO 0);
SIGNAL address_out_2    : unsigned(1 DOWNTO 0);
SIGNAL address_out_3    : unsigned(1 DOWNTO 0);
SIGNAL address_out_4    : unsigned(1 DOWNTO 0);
SIGNAL address_out_5    : unsigned(1 DOWNTO 0);
SIGNAL aout_10          : unsigned(13 DOWNTO 0);
SIGNAL aout_3           : unsigned(13 DOWNTO 0);
SIGNAL aout_4           : unsigned(13 DOWNTO 0);
SIGNAL aout_5           : unsigned(13 DOWNTO 0);
SIGNAL aout_6           : unsigned(13 DOWNTO 0);
SIGNAL aout_7           : unsigned(13 DOWNTO 0);
SIGNAL aout_8           : unsigned(13 DOWNTO 0);
SIGNAL aout_9           : unsigned(13 DOWNTO 0);
SIGNAL clk1             : std_ulogic;
SIGNAL clk1out          : std_ulogic;
SIGNAL clk1out_1        : std_ulogic;
SIGNAL clk1out_2        : std_ulogic;
SIGNAL clk1out_3        : std_ulogic;
SIGNAL clk1out_4        : std_ulogic;
SIGNAL clk1out_5        : std_ulogic;
SIGNAL clk2             : std_ulogic;
SIGNAL clk2out          : std_ulogic;
SIGNAL clk2out_1        : std_ulogic;
SIGNAL clk2out_2        : std_ulogic;
SIGNAL clk2out_3        : std_ulogic;
SIGNAL clk2out_4        : std_ulogic;
SIGNAL clk_2            : std_ulogic;
SIGNAL compl            : std_ulogic;
SIGNAL compl_1          : std_ulogic;
SIGNAL compl_out        : std_ulogic;
SIGNAL compl_out_1      : std_ulogic;
SIGNAL compl_out_2      : std_ulogic;
SIGNAL compl_out_3      : std_ulogic;
SIGNAL compl_out_4      : std_ulogic;
SIGNAL d_in             : unsigned(6 DOWNTO 0);
SIGNAL d_in_1           : unsigned(6 DOWNTO 0);
SIGNAL d_out            : unsigned(6 DOWNTO 0);
SIGNAL d_out_1          : unsigned(6 DOWNTO 0);
SIGNAL d_out_2          : unsigned(6 DOWNTO 0);
SIGNAL d_out_3          : unsigned(6 DOWNTO 0);
SIGNAL d_out_4          : unsigned(6 DOWNTO 0);
SIGNAL d_out_5          : unsigned(6 DOWNTO 0);
SIGNAL enable           : std_ulogic;
SIGNAL enable0          : std_ulogic;
SIGNAL enable1          : std_ulogic;
SIGNAL enable_1         : std_ulogic;
SIGNAL enable_1_out     : std_ulogic;
SIGNAL enable_1_out_1   : std_ulogic;
SIGNAL enable_1_out_2   : std_ulogic;
SIGNAL enable_1_out_3   : std_ulogic;
SIGNAL enable_1_out_4   : std_ulogic;
SIGNAL enable_2         : std_ulogic;
SIGNAL enable_out       : std_ulogic;
SIGNAL enable_out_1     : std_ulogic;
SIGNAL enable_out_2     : std_ulogic;
SIGNAL enable_out_3     : std_ulogic;
SIGNAL enable_out_4     : std_ulogic;
SIGNAL enable_rom       : std_ulogic;
SIGNAL enable_rom_1     : std_ulogic;
SIGNAL enable_rom_2     : std_ulogic;
SIGNAL enable_rom_out   : std_ulogic;
SIGNAL enable_rom_out_1 : std_ulogic;
SIGNAL enable_rom_out_2 : std_ulogic;
SIGNAL enable_rom_out_3 : std_ulogic;
SIGNAL enable_rom_out_4 : std_ulogic;
SIGNAL reset0           : std_ulogic;
SIGNAL reset_out        : std_ulogic;
SIGNAL reset_out_1      : std_ulogic;
SIGNAL reset_out_2      : std_ulogic;
SIGNAL reset_out_3      : std_ulogic;
SIGNAL reset_out_4      : std_ulogic;
SIGNAL temp             : unsigned(27 DOWNTO 0);
SIGNAL temp1            : unsigned(41 DOWNTO 0);
SIGNAL temp2            : unsigned(55 DOWNTO 0);

-- Component Declarations
COMPONENT MACX00
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACX01
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACX02
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACX03
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACXe0
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACXe1
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      clk_2      : IN     std_ulogic ;
      compl      : IN     std_ulogic ;
      enable     : IN     std_ulogic ;
      enable_1   : IN     std_ulogic ;
      enable_2   : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT MACXe2
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      clk        : IN     std_ulogic ;
      clk_1      : IN     std_ulogic ;
      cl