dct8_medium.vhd

来自「算术处理器的VERILOG hdl的源代码」· VHDL 代码 · 共 2,683 行 · 第 1/5 页

USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY MACX03 IS
   PORT( 
      addr2      : IN     unsigned (1 DOWNTO 0) ;
      clk        : IN     std_ulogic  ;
      clk_1      : IN     std_ulogic  ;
      clk_2      : IN     std_ulogic  ;
      compl      : IN     std_ulogic  ;
      enable     : IN     std_ulogic  ;
      enable_1   : IN     std_ulogic  ;
      enable_2   : IN     std_ulogic  ;
      enable_rom : IN     std_ulogic  ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );

-- Declarations

END MACX03 ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF MACX03 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL Sout      : unsigned(11 DOWNTO 0);
SIGNAL aout      : unsigned(11 DOWNTO 0);
SIGNAL aout_1    : unsigned(12 DOWNTO 0);
SIGNAL aout_2    : unsigned(13 DOWNTO 0);
SIGNAL bin       : unsigned(13 DOWNTO 0);
SIGNAL coeff_out : unsigned(11 downto 0);
SIGNAL output    : unsigned(12 DOWNTO 0);
SIGNAL output_1  : unsigned(13 DOWNTO 0);

-- Component Declarations
COMPONENT ROMC_03
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      compl      : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      coeff_out  : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add12signed
   PORT (
      a      : IN     unsigned (11 DOWNTO 0);
      b      : IN     unsigned (11 DOWNTO 0);
      output : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add14signed
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      bin    : IN     unsigned (13 DOWNTO 0);
      output : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT div2
   PORT (
      Sin  : IN     unsigned (12 downto 0);
      Sout : OUT    unsigned (11 downto 0)
   );
END COMPONENT;
COMPONENT reg12b
   PORT (
      ain    : IN     unsigned (11 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg13b
   PORT (
      ain    : IN     unsigned (12 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg14b
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;

-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROMC_03 USE ENTITY work.ROMC_03;
FOR ALL : add12signed USE ENTITY work.add12signed;
FOR ALL : add14signed USE ENTITY work.add14signed;
FOR ALL : div2 USE ENTITY work.div2;
FOR ALL : reg12b USE ENTITY work.reg12b;
FOR ALL : reg13b USE ENTITY work.reg13b;
FOR ALL : reg14b USE ENTITY work.reg14b;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
bin <= aout_1(12)&aout_1;


   -- Instance port mappings.
   I0 : ROMC_03
      PORT MAP (
         addr2      => addr2,
         compl      => compl,
         enable_rom => enable_rom,
         coeff_out  => coeff_out
      );
   I3 : add12signed
      PORT MAP (
         a      => Sout,
         b      => aout,
         output => output
      );
   I6 : add14signed
      PORT MAP (
         ain    => aout_2,
         bin    => bin,
         output => output_1
      );
   I5 : div2
      PORT MAP (
         Sin  => aout_1,
         Sout => Sout
      );
   I2 : reg12b
      PORT MAP (

         ain    => coeff_out,
         clk    => clk,
         enable => enable,
         aout   => aout
      );
   I4 : reg13b
      PORT MAP (
         ain    => output,
         clk    => clk,
         enable => enable,
         aout   => aout_1
      );
   I7 : reg14b
      PORT MAP (
         ain    => output_1,
         clk    => clk_1,
         enable => enable_1,
         aout   => aout_2
      );
   I8 : reg14b
      PORT MAP (
         ain    => aout_2,
         clk    => clk_2,
         enable => enable_2,
         aout   => aout_3
      );

END struct;

--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY MACXe0 IS
   PORT( 
      addr2      : IN     unsigned (1 DOWNTO 0) ;
      clk        : IN     std_ulogic  ;
      clk_1      : IN     std_ulogic  ;
      clk_2      : IN     std_ulogic  ;
      compl      : IN     std_ulogic  ;
      enable     : IN     std_ulogic  ;
      enable_1   : IN     std_ulogic  ;
      enable_2   : IN     std_ulogic  ;
      enable_rom : IN     std_ulogic  ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );

-- Declarations

END MACXe0 ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF MACXe0 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL Sout      : unsigned(11 DOWNTO 0);
SIGNAL aout      : unsigned(11 DOWNTO 0);
SIGNAL aout_1    : unsigned(12 DOWNTO 0);
SIGNAL aout_2    : unsigned(13 DOWNTO 0);
SIGNAL bin       : unsigned(13 DOWNTO 0);
SIGNAL coeff_out : unsigned(11 downto 0);
SIGNAL output    : unsigned(12 DOWNTO 0);
SIGNAL output_1  : unsigned(13 DOWNTO 0);

-- Component Declarations
COMPONENT ROMC_e0
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      compl      : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      coeff_out  : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add12signed
   PORT (
      a      : IN     unsigned (11 DOWNTO 0);
      b      : IN     unsigned (11 DOWNTO 0);
      output : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add14signed
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      bin    : IN     unsigned (13 DOWNTO 0);
      output : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT div2
   PORT (
      Sin  : IN     unsigned (12 downto 0);
      Sout : OUT    unsigned (11 downto 0)
   );
END COMPONENT;
COMPONENT reg12b
   PORT (
      ain    : IN     unsigned (11 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg13b
   PORT (
      ain    : IN     unsigned (12 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg14b
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;

-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROMC_e0 USE ENTITY work.ROMC_e0;
FOR ALL : add12signed USE ENTITY work.add12signed;
FOR ALL : add14signed USE ENTITY work.add14signed;
FOR ALL : div2 USE ENTITY work.div2;
FOR ALL : reg12b USE ENTITY work.reg12b;
FOR ALL : reg13b USE ENTITY work.reg13b;
FOR ALL : reg14b USE ENTITY work.reg14b;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
bin <= aout_1(12)&aout_1;


   -- Instance port mappings.
   I0 : ROMC_e0
      PORT MAP (
         addr2      => addr2,
         compl      => compl,
         enable_rom => enable_rom,
         coeff_out  => coeff_out
      );
   I3 : add12signed
      PORT MAP (
         a      => Sout,
         b      => aout,
         output => output
      );
   I6 : add14signed
      PORT MAP (
         ain    => aout_2,
         bin    => bin,
         output => output_1
      );
   I5 : div2
      PORT MAP (
         Sin  => aout_1,
         Sout => Sout
      );
   I2 : reg12b
      PORT MAP (

         ain    => coeff_out,
         clk    => clk,
         enable => enable,
         aout   => aout
      );
   I4 : reg13b
      PORT MAP (
         ain    => output,
         clk    => clk,
         enable => enable,
         aout   => aout_1
      );
   I7 : reg14b
      PORT MAP (
         ain    => output_1,
         clk    => clk_1,
         enable => enable_1,
         aout   => aout_2
      );
   I8 : reg14b
      PORT MAP (
         ain    => aout_2,
         clk    => clk_2,
         enable => enable_2,
         aout   => aout_3
      );

END struct;

--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY MACXe1 IS
   PORT( 
      addr2      : IN     unsigned (1 DOWNTO 0) ;
      clk        : IN     std_ulogic  ;
      clk_1      : IN     std_ulogic  ;
      clk_2      : IN     std_ulogic  ;
      compl      : IN     std_ulogic  ;
      enable     : IN     std_ulogic  ;
      enable_1   : IN     std_ulogic  ;
      enable_2   : IN     std_ulogic  ;
      enable_rom : IN     std_ulogic  ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );

-- Declarations

END MACXe1 ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY work;

ARCHITECTURE struct OF MACXe1 IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL Sout      : unsigned(11 DOWNTO 0);
SIGNAL aout      : unsigned(11 DOWNTO 0);
SIGNAL aout_1    : unsigned(12 DOWNTO 0);
SIGNAL aout_2    : unsigned(13 DOWNTO 0);
SIGNAL bin       : unsigned(13 DOWNTO 0);
SIGNAL coeff_out : unsigned(11 downto 0);
SIGNAL output    : unsigned(12 DOWNTO 0);
SIGNAL output_1  : unsigned(13 DOWNTO 0);

-- Component Declarations
COMPONENT ROMC_e1
   PORT (
      addr2      : IN     unsigned (1 DOWNTO 0);
      compl      : IN     std_ulogic ;
      enable_rom : IN     std_ulogic ;
      coeff_out  : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add12signed
   PORT (
      a      : IN     unsigned (11 DOWNTO 0);
      b      : IN     unsigned (11 DOWNTO 0);
      output : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT add14signed
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      bin    : IN     unsigned (13 DOWNTO 0);
      output : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;
COMPONENT div2
   PORT (
      Sin  : IN     unsigned (12 downto 0);
      Sout : OUT    unsigned (11 downto 0)
   );
END COMPONENT;
COMPONENT reg12b
   PORT (
      ain    : IN     unsigned (11 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (11 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg13b
   PORT (
      ain    : IN     unsigned (12 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (12 DOWNTO 0)
   );
END COMPONENT;
COMPONENT reg14b
   PORT (
      ain    : IN     unsigned (13 DOWNTO 0);
      clk    : IN     std_ulogic ;
      enable : IN     std_ulogic ;
      aout   : OUT    unsigned (13 DOWNTO 0)
   );
END COMPONENT;

-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROMC_e1 USE ENTITY work.ROMC_e1;
FOR ALL : add12signed USE ENTITY work.add12signed;
FOR ALL : add14signed USE ENTITY work.add14signed;
FOR ALL : div2 USE ENTITY work.div2;
FOR ALL : reg12b USE ENTITY work.reg12b;
FOR ALL : reg13b USE ENTITY work.reg13b;
FOR ALL : reg14b USE ENTITY work.reg14b;
--synopsys translate_on

BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
bin <= aout_1(12)&aout_1;


   -- Instance port mappings.
   I0 : ROMC_e1
      PORT MAP (
         addr2      => addr2,
         compl      => compl,
         enable_rom => enable_rom,
         coeff_out  => coeff_out
      );
   I3 : add12signed
      PORT MAP (
         a      => Sout,
         b      => aout,
         output => output
      );
   I6 : add14signed
      PORT MAP (
         ain    => aout_2,
         bin    => bin,
         output => output_1
      );
   I5 : div2
      PORT MAP (
         Sin  => aout_1,
         Sout => Sout
      );
   I2 : reg12b
      PORT MAP (

         ain    => coeff_out,
         clk    => clk,
         enable => enable,
         aout   => aout
      );
   I4 : reg13b
      PORT MAP (
         ain    => output,
         clk    => clk,
         enable => enable,
         aout   => aout_1
      );
   I7 : reg14b
      PORT MAP (
         ain    => output_1,
         clk    => clk_1,
         enable => enable_1,
         aout   => aout_2
      );
   I8 : reg14b
      PORT MAP (
         ain    => aout_2,
         clk    => clk_2,
         enable => enable_2,
         aout   => aout_3
      );

END struct;

--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY MACXe2 IS
   PORT( 
      addr2      : IN     unsigned (1 DOWNTO 0) ;
      clk        : IN     std_ulogic  ;
      clk_1      : IN     std_ulogic  ;
      clk_2      : IN     std_ulogic  ;
      compl      : IN     std_ulogic  ;
      enable     : IN     std_ulogic  ;
      enable_1   : IN     std_ulogic  ;
      enable_2   : IN     std_ulogic  ;
      enable_rom : IN     std_ulogic  ;
      aout_3     : OUT    unsigned (13 DOWNTO 0)
   );

-- Declarations