data_path.v

使用Verilog语言编写

`timescale 1ns/100ps
module data_path( data,
                  count1,count2,count3,count4,count5,count6,count7,count8,
                  datar_out0,datar_out1,datar_out2,datar_out3,
	          fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs,
		  inter_pos0,inter_pos1,inter_pos2,inter_pos3 );

input [3:0]  count1,count2,count3,count4,count5,count6,count7,count8;
input [7:0] datar_out0,datar_out1,datar_out2,datar_out3;//4个读取数据
input fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs;//4个接收FIFO读取命令
input inter_pos0,inter_pos1,inter_pos2,inter_pos3;//4个中断状态位读取命令

output [7:0] data;
wire [7:0] pos0 = {count1,count2};
wire [7:0] pos1 = {count3,count4};
wire [7:0] pos2 = {count5,count6};
wire [7:0] pos3 = {count7,count8};

assign data = inter_pos0 ?  pos0 : (inter_pos1 ?  pos1 : (inter_pos2 ?  pos2 : (inter_pos3 ? pos3 : ( fifor0_cs ? datar_out0 : (fifor1_cs ? datar_out1 : (fifor2_cs ? datar_out2 : (fifor3_cs ? datar_out3 : 8'bz)))))));

endmodule