rcvr_lattice.v

使用Verilog语言编写

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_receiver.v                                             ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module rcvr ( clk,rst,rxd,baud_clk,baud_clk1,
              fifor_cs,
              data_out,EF,AE,AF,FF,rbr) ;  //接收模块

input clk,rst ;
input baud_clk,baud_clk1;
input fifor_cs;
input rxd ;  //接收串口数据

output [7:0] data_out; //输出到8位总线
output EF,AE,AF,FF;


wire baud_clk ;
wire [7:0] data_out1;
reg [7:0] data_out;

reg wr; 
reg tmp;
reg pop;

always @(posedge clk or posedge rst ) 
if(rst) tmp <= 0 ;
else tmp <= fifor_cs;

always @(posedge clk or posedge rst ) 
if(rst) pop <= 0 ;
else if(!EF) pop <= fifor_cs & ~tmp; //保护FIFO不会溢出错误

always @(posedge clk ) if(pop) data_out <= data_out1 ;

UART_FIFO u1( .clk( clk ),
              .rst( rst ),
		      .data_in( rbr ),
		      .data_out( data_out1 ),
		      .push( rf_push ),
		      .pop(pop),
		      .EF( EF ),
		      .AE( AE ),
		      .AF( AF ),
		      .FF( FF )
		    );




wire 		rcounter16_eq_7 = (rcounter16 == 4'd7);
wire		rcounter16_eq_0 = (rcounter16 == 4'd0);
wire		rcounter16_eq_1 = (rcounter16 == 4'd1);

wire [3:0] rcounter16_minus_1 = rcounter16 - 4'd1;

parameter  sr_idle        = 2'd0;
parameter  sr_rec_bit     = 2'd2;
parameter  sr_rec_parity  = 2'd3;
parameter  sr_rec_stop    = 2'd1;

always @(posedge clk)	srx_pad_i_reg <= rxd;
	   
always @(posedge clk or posedge rst)
begin
  if (wb_rst_i)
  begin
     rstate 	<=  sr_idle;
     rcounter16 <=   0;
     rbit_counter <=   0;
     rf_push 	<=   1'b0;
     rf_data_in <=   8'b0;
  end
  else
  begin
  if (enable)
  begin
	case (rstate)
	sr_idle :	begin
	                   if (!srx_pad_i && srx_pad_i_reg)   
	                      rcounter16 <=   4'b1110;
	                   else if (!srx_pad_i)
	                      rcounter16 <= rcounter16 - 1;
	                   else
	                      rcounter16 <= 4'b0;
	                             
	                   if (!srx_pad_i && rcounter16_eq_7)   
				rstate <=   sr_rec_bit;
				
			   rbit_counter <=   3'b111;	
		           //rparity <= par_e_o;	
		           rf_push    <=   1'b0;	
                        end
	sr_rec_bit :	begin
				if (rcounter16_eq_7) // read the bit
				begin
				    rf_data_in[7:0]  <=   {srx_pad_i, rf_data_in[7:1]};//receiving
				    if (rbit_counter==3'b0) // no more bits in word
					rstate <=sr_rec_stop; //no parity bit
                                    else
                                       	rbit_counter <=   rbit_counter - 3'b1;		
                                end                                       				
				rcounter16 <=   rcounter16_minus_1;
			end
	sr_rec_stop :	begin
                           if (rcounter16_eq_7)	
                           begin
                              if (srx_pad_i)
                                rf_push    <=   1'b1;
                              else
                                rf_push    <=   1'b0;
                           
                              rstate <=   sr_idle;					
                           end				
                           
                           rcounter16 <=   rcounter16_minus_1;
                        end
        default : rstate <=   sr_idle;
        endcase
  end  // if (enable)
  end //end else
end // always of receiver

endmodule