txmit.v

使用Verilog语言编写

`timescale 1 ns / 100ps

module txmit ( clk,rst,data,we,baud_clk,
               sdo,EF,AE,AF,FF,count
             ) ;  //发送模块

output sdo ;//serial data output
output EF,AE,AF,FF; 
input [7:0] data;
input clk , rst ;
input we ;  //FIFO片选信号
input baud_clk;   //串口传送波特率时钟
output [3:0] count;

wire [7:0] tsr_tmp ; //作移位输出到SDO使用
reg [7:0] tsr;
reg sdo ;

reg [3:0] no_bits_sent ;   //控制串出数据顺序
reg rd;
wire  EF,AE,AF,FF;

reg tmp; 
reg we_en;

always @(posedge clk or posedge rst) 
if(rst) tmp <= 0 ;
else begin
     tmp<= we ;
     end

always @(posedge clk) we_en <= !FF & we & ~tmp ;//we&~tmp generate a short pulse

UART_FIFO u0( .clk( clk ),
              .rst( rst ),
              .data_in( data ),
	          .data_out( tsr_tmp ),
	          .push( we_en ),
	          .pop( rd ),
	          .EF( EF ),
	          .AE( AE ),
	          .AF( AF ),
	          .FF( FF ),
              .count(count)
              );
              
reg flag;
always @(posedge clk or posedge rst)
if(rst) flag <= 0 ;
else flag <= no_bits_sent == 4'b1101 ;//

always @(posedge baud_clk or posedge rst)
if (rst)     begin
             sdo <= 1'b1 ;
             tsr <= 8'b0 ;
             end
else   if(!EF)      begin  if(no_bits_sent == 4'b0001) tsr <= tsr_tmp;
                    else if( no_bits_sent == 4'b0010 ) sdo <= 0 ;
                    else if ((no_bits_sent >= 4'b0011) && (no_bits_sent <= 4'b1010))
                    begin
                    tsr[6:0] <= tsr[7:1] ;
                    tsr[7] <= 1'b0 ;
                    sdo <= tsr[0] ; //串出数据bit 0,bit 1,...bit 7
                    end
                    else  sdo<= 1'b1;//  sdo <= 1'b1 if (no_bits_sent == 4'b1011) ;
                    end
		else sdo <= 1'b1;

reg state ;

always @(posedge clk or posedge rst)
  if(rst)   begin
            state <= 0;
            rd <= 0 ;
        end
  else  begin
           case(state)
		0 : if( flag ) begin
		               rd <= 1;
			       state <= 1 ;
 			       end
                1 : begin
		    rd <= 0 ;
                    if( !flag ) state <= 0;
		     end
            endcase
        end



always @(posedge baud_clk or posedge rst )
if (rst)    no_bits_sent <= 4'b0000 ;
else if ( flag|EF )  no_bits_sent <= 4'b0000 ;
     else no_bits_sent <= no_bits_sent + 1 ; 
     
endmodule