baud1.v

使用Verilog语言编写

module baud(clk,rst,baud_clk,clk16x);

input clk ;
input rst ;
output baud_clk ;
output reg clk16x ;

reg [5:0] cnt_16x ;
reg [3:0] baud_clk_cnt ; 

always @(posedge clk or posedge rst)
if(rst) begin
        cnt_16x <= 0 ;
        clk16x <= 0 ;
		end
else if( cnt_16x =='d35 ) begin
                           cnt_16x <= 0;
                           clk16x <= ~clk16x ;
						   end
     else cnt_16x <= cnt_16x + 1;

//assign clk16x = (cnt_16x < 'd36) ? 1'b1 : 1'b0;

always @(posedge clk16x or posedge rst)
   if (rst)      baud_clk_cnt <= 0;
   else   baud_clk_cnt <= baud_clk_cnt + 1;
            
assign baud_clk = baud_clk_cnt[3];

endmodule