uart4_top_tb.v

来自「使用Verilog语言编写」· Verilog 代码 · 共 74 行

`timescale 1ns/100ps

module uart_top_tb ;

	reg clk;
	reg rst;
	reg [4:0] addr;
	reg cs_n;
	reg we_n;
	reg oe_n;
	reg [3:0] rxd;


// Outputs
	wire inter;
	wire [3:0] txd;
	wire [7:0] rsr;
	wire [7:0] data;
        wire clk_out ;

parameter clock = 100 ; 

	Uart4 UUT (
		.clk(clk), 
		.rst(rst), 
		.addr(addr), 
		.data(data), 
		.cs_n(cs_n), 
		.inter(inter), 
		.we_n(we_n), 
		.oe_n(oe_n), 
		.rxd(rxd), 
		.txd(txd), 
		.rsr(rsr),
		.clk_out(clk_out)
	);


	initial begin
		clk = 0 ;
		forever #(clock/2) clk = ~clk ;
		end
		
	initial begin	
		rst = 0 ;
		#50 rst = 1 ;
		#100 rst = 0 ;
		end
		
	initial begin	
		addr = 0;
		
		end
		
	initial begin	
		cs_n = 0;
		
		end
		
	initial begin	
		we_n = 0;
		
		end
		
	initial begin	
		oe_n = 0;
		
		end
		
	initial begin	
		rxd = 0;
	        end
	
	endmodule