rcvr.v

使用Verilog语言编写

`timescale 1 ns / 100ps

module rcvr ( clk,clk16x,rst,rxd,
              rd,//cpu读信号
              data_out,EF,AE,AF,FF,count) ;  //接收模块

input clk,rst ;
input clk16x;
input rd;
input rxd ;  //串口接收数据
output [7:0] data_out; //输出到8位总线
output EF,AE,AF,FF;   

output [3:0] count;
reg rxd1,rxd2 ;
reg [7:0] rsr ; 
reg push; 
reg tmp ;
reg pop;
reg wr;

always @(posedge clk or posedge rst ) 
if(rst) tmp <= 0 ;
else begin
     tmp <= rd;                        
     end

always @(posedge clk or posedge rst ) 
if(rst) pop <= 0 ;
else pop <=  ~rd & tmp ; //保护FIFO不会溢出错误

UART_FIFO u1( .clk( clk ),
              .rst( rst ),
	          .data_in( rsr ),
	          .data_out( data_out ),
	          .push( wr ),
	          .pop( pop ),
	          .EF( EF ),
	          .AE( AE ),
	          .AF( AF ),
	          .FF( FF ),
              .count(count)
	        );

always @(posedge clk16x or posedge rst)
if (rst)   begin
           rxd1 <= 1'b1 ; 
           rxd2 <= 1'b1 ;
           end
else       begin
           rxd1 <= rxd ;
           rxd2 <= rxd1 ;
           end

reg [1:0] state;
reg [2:0] bit_count;
reg [3:0] rev_count;

wire  rev_count_7 = rev_count == 4'b0111;

parameter idle = 0, rev = 1 , rev_stop = 2,delay = 3;
   
always @(posedge clk16x or posedge rst)
if(rst) begin
        state <= 0;
        bit_count <= 0;
        rev_count <= 0;
        rsr <= 0;
        push <= 0;
        end
else    begin
        case(state)
        idle  :  begin
                 if (!rxd1 && rxd2)   rev_count <=   4'b1101;
	             else if (!rxd)   rev_count <= rev_count - 1;
	                  else    rev_count <= 4'b0;
	             if (!rxd && rev_count_7)  state <= rev ;
	             bit_count <= 3'b111 ;	
		         push <= 1'b0 ;
		         end
        rev   :  begin
                            if (rev_count_7) 	begin
				                                rsr[7:0] <= {rxd, rsr[7:1]};//receiving
				                                if (bit_count == 3'b0) 	state <= rev_stop;// no more bits in word
                                                else bit_count <= bit_count - 1;
                                                end                                       				
		         rev_count <= rev_count - 1;
                 end
     rev_stop :   begin
                            if (rev_count_7)	begin
                                                if(rxd) push <= 1'b1;
												else push <= 1'b0;
                                                state <= idle;					
                                                end				
                                                rev_count <= rev_count - 1;
                                                end
      default : state <= idle;
        endcase
        end

reg state1;

always @(posedge clk or posedge rst)
if(rst) begin
        state1 <= 0 ;
        wr <= 0;
        end
else begin
     case(state1) 
     0  : if(push)  begin
                     wr <= 1 ;
                     state1 <= 1 ;
                     end		 
     1  : begin
          wr <= 0 ;
          if(!push) state1 <= 0 ;
          end
     endcase
     end

endmodule