uart4_top.v

使用Verilog语言编写

`timescale 1ns/100ps

module Uart4( clk,rst,addr,data,cs_n,inter,we_n,oe_n,rxd,txd,rsr,clk_out);

input clk ;    //Main clock
input rst;
input [4:0] addr;
inout [7:0] data;
input cs_n,we_n,oe_n;
output clk_out;

output inter;
input  rxd;
output txd;
output [7:0] rsr;


/////////////////////////////////////////////////////////////////////////////////////////////////////
wire fifot0_cs;//,fifot1_cs,fifot2_cs,fifot3_cs;
wire fifor0_cs;//,fifor1_cs,fifor2_cs,fifor3_cs;
wire baud_cs0;//,baud_cs1,baud_cs2,baud_cs3;

decode u1( clk,addr,data,cs_n,we_n,oe_n,//input
           baud_cs0,baud_cs1,baud_cs2,baud_cs3,
           fifot0_cs,fifot1_cs,fifot2_cs,fifot3_cs,
		   fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs,
		   inter_pos0,inter_pos1,inter_pos2,inter_pos3,inter_pos4,inter_pos5,inter_pos6,inter_pos7,
           inter_mask
          );
          
wire clk16x/*synthesis syn_keep = 1*/;
wire baud_clk /*synthesis syn_keep = 1*/;

assign clk_out = baud_clk ;
baud u2(clk,rst,baud_clk,clk16x);
/////////////////////////////////////////////////////////////////////////////////////////////////////
wire EF0,AE0,AF0,FF0;
//wire EF1,AE1,AF1,FF1;
//wire EF2,AE2,AF2,FF2;
//wire EF3,AE3,AF3,FF3;
wire [3:0] count1;//,count2,count3,count4;

txmit u3( clk,rst,data,fifot0_cs,baud_clk,txd[0],EF0,AE0,AF0,FF0,count1 ) ;

//txmit u4( clk,rst,data,fifot1_cs,baud_clk,txd[1],EF1,AE1,AF1,FF1,count2 ) ;
//
//txmit u5( clk,rst,data,fifot2_cs,baud_clk,txd[2],EF2,AE2,AF2,FF2,count3 ) ;
//
//txmit u6( clk,rst,data,fifot3_cs,baud_clk,txd[3],EF3,AE3,AF3,FF3,count4 ) ;

//////////////////////////////////////////////////////////////////////////////////////////////
wire EF4,AE4,AF4,FF4;
//wire EF5,AE5,AF5,FF5;
//wire EF6,AE6,AF6,FF6;
//wire EF7,AE7,AF7,FF7;
wire [7:0] datar_out0;//,datar_out1,datar_out2,datar_out3;
wire [3:0] count5;//,count6,count7,count8;

rcvr u7(clk,clk16x,rst,rxd[0],fifor0_cs,datar_out0,EF4,AE4,AF4,FF4,count5);

//rcvr u8(clk,clk16x,rst,rxd[1],fifor1_cs,datar_out1,EF5,AE5,AF5,FF5,count6);
//
//rcvr u9(clk,clk16x,rst,rxd[2],fifor2_cs,datar_out2,EF6,AE6,AF6,FF6,count7);
//
//rcvr u10(clk,clk16x,rst,rxd[3],fifor3_cs,datar_out3,EF7,AE7,AF7,FF7,count8);

///////////////////////////////////
  inter u12 (  clk,addr,data,
               AE0,AF0,EF0,AE1,AF1,EF1,AE2,AF2,EF2,AE3,AF3,EF3,AF4,FF4,AF5,FF5,AF6,FF6,AF7,FF7,
		       inter_mask,inter   //output
             );             
             
 assign rsr = {count5,count1};
/////////////////////////////////////////////////////////////////////
data_path u13 (   data,
                  count1,count2,count3,count4,count5,count6,count7,count8,
                  datar_out0,datar_out1,datar_out2,datar_out3,
			      fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs,
			      inter_pos0,inter_pos1,inter_pos2,inter_pos3
               );

endmodule