s_to_p.v.bak

一个用verilog写的串行传输到并行传输的程序

`timescale  1ns/1ns
module s_to_p(clk,rst,mode,rec_en,sen_en,ser_in,data);
    input clk;
    input rst;
    input mode;
    input rec_en;
    input sen_en;
    input ser_in;
    
    output [7:0] data;
    
    
    reg[3:0] state;
    reg[7:0] databuf;
    reg      ready;
    
    parameter   idle=4'b0000,
                bit7=4'b0001,
                bit6=4'b0010,
                bit5=4'b0011,
                bit4=4'b0100,
                bit3=4'b0101,
                bit2=4'b0110,
                bit1=4'b0111,
                bit0=4'b1000;
               // out1=4'b1001;
   //assign data[7]=ready?databuf[7]:1'bz;
   assign data=ready?databuf:data;
    
    always @ (posedge clk or negedge rst)
       if (!rst)
          begin
              databuf<=8'bxxxx_xxxx;
              state<=idle;
              ready<=1'b0;
          end
        else if (mode)
           begin
               case (state)
               idle:   if (rec_en)
                   begin
                       ready<=1'b0;
                       databuf[0]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit7;
                   end
                   else    state<= idle;
                bit7:   if (rec_en)
                   begin
                       databuf[1]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit6;
                   end
                   else    state<= idle;
                 bit6:  if  (rec_en)
                   begin
                       databuf[2]<= ser_in;
                      // databuf<= databuf>>1;
                       state<= bit5;
                   end
                   else    state<= idle;
                 bit5:   if (rec_en)
                   begin
                       databuf[3]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit4;
                   end
                   else    state<= idle;
                 bit4:   if (rec_en)
                   begin
                       databuf[4]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit3;
                   end
                   else    state<= idle;
                 bit3:   if (rec_en)
                   begin
                       databuf[5]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit2;
                   end
                   else    state<= idle;
                 bit2:   if (rec_en)
                   begin
                       databuf[6]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= bit1;
                   end
                   else    state<= idle;
                 bit1:   if (rec_en)
                   begin
                       databuf[7]<= ser_in;
                       //databuf<= databuf>>1;
                       state<= idle;
                       if (sen_en)  ready<=1'b1;
                       else   ready<=1'b0;
                   end
                   else    state<= idle;
                 //bit0:  // if (rec_en)
                   //begin
                       //databuf[7]<= data[7];
                   //    databuf<= databuf>>1;
                    //   state<= out1;
                  // end
                  // else    state<= idle;
               // out1: 
                  // if (sen_en)
                   // begin
                     //   ready<=1'b1;
                    //    state<=idle;
                  //  end
                 //   else   state<=idle;
                default:   state<=idle;
                endcase              
           end
endmodule