_primary.vhd

一个用verilog写的串行传输到并行传输的程序

library verilog;
use verilog.vl_types.all;
entity s_to_p is
    generic(
        idle            : integer := 0;
        bit7            : integer := 1;
        bit6            : integer := 2;
        bit5            : integer := 3;
        bit4            : integer := 4;
        bit3            : integer := 5;
        bit2            : integer := 6;
        bit1            : integer := 7;
        bit0            : integer := 8
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        mode            : in     vl_logic;
        rec_en          : in     vl_logic;
        sen_en          : in     vl_logic;
        ser_in          : in     vl_logic;
        data            : out    vl_logic_vector(7 downto 0)
    );
end s_to_p;