divarrsgn_tb.v

来自「用VHDL实现的除法器,非常好使,仿真通过了」· Verilog 代码 · 共 41 行

//---------------------------auther :JHxin-------------------------------//

`timescale 1ns/100ps
module DivArrUns_tb();
reg[15:0]  x;
reg[7:0]   y;
wire[8:0]   q;
wire[7:0]   r;

DivArrUns  div(
               .X(x),
               .Y(y),
               .Q(q),
               .R(r)
               );
               
initial
  begin
    x = 16'd15;
    y = 8'd7;
    #10
    x = 16'd9;
    y = 8'd3;
    #10
    x = 16'd21;
    y = 8'd7;
    #10
    x = 16'd100;
    y = 8'd33;
    #10
    x = 16'd1000;
    y = 8'd369;
    #10
    x = 16'd50;
    y = 8'd9;
    #10
    x = 16'd100;
    y = 8'd50;
  end
endmodule