arith_lib.vhd

来自「用VHDL实现的除法器,非常好使,仿真通过了」· VHDL 代码 · 共 44 行

-------------------------------------------------------------------------------
-- Description :
-- Package containing all component declarations.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.arith_utils.all;

package arith_lib is

  --type integer is (slow, medium, fast);

  -----------------------------------------------------------------------------
  -- Dividers / Square Root Extractors
  -----------------------------------------------------------------------------
  component DivArrUns
    generic (widthX : integer;
	     widthY : integer);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  Q : out std_logic_vector(widthX-widthY downto 0);
	  R : out std_logic_vector(widthY-1 downto 0));
  end component;

  

  component FullAdder
    port (A, B, CI : in std_logic;
	  S, CO : out std_logic);
  end component;

  component ad01d1
    port (A, B, CI : in std_logic;
	  S, CO : out std_logic);
  end component;

end arith_lib;

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