divarruns.vhd

用VHDL实现的除法器,非常好使,仿真通过了

-------------------------------------------------------------------------------
-- Description :
-- Restoring array divider for unsigned numbers. Divisor must be normalized
-- (i.e. Y(widthY-1) = '1')
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.arith_lib.all;

-------------------------------------------------------------------------------

entity DivArrUns is

  generic (widthX : integer := 16;	-- word width of X
	         widthY : integer := 8);	-- word width of Y

  port (X : in std_logic_vector(widthX-1 downto 0);  -- dividend32
	      Y : in std_logic_vector(widthY-1 downto 0);  -- divisor, normalized16
        Q : out std_logic_vector(widthX-widthY downto 0);  -- quotient17
        R : out std_logic_vector(widthY-1 downto 0));  -- remainder16

end DivArrUns;

-------------------------------------------------------------------------------

architecture Structural of DivArrUns is

  constant widthQ : integer := widthX-widthY+1;  -- word width of Q  17

  signal YI : std_logic_vector(widthY downto 0);  -- inverted Y 17bits
  signal ST : std_logic_vector(widthQ*(widthY+1)-1 downto 0);  -- sums 289 bits
  signal RT : std_logic_vector((widthQ+1)*(widthY+2)-1 downto 0); -- remainders  324 bits
  signal CT : std_logic_vector(widthQ*(widthY+2)-1 downto 0);  -- carries 306 bits

begin
  -- invert divisor Y for subtraction
  YI <= '1' & not Y;  
  -- first partial remainder is dividend X 
  RT(widthQ*(widthY+2)+widthY downto widthQ*(widthY+2)+1) <=
    '0' & X(widthX-1 downto widthX-widthY+1);
    
-----------------------------------------------------------------------
  -- process one row for each quotient bit
  row : for k in widthQ-1 downto 0 generate  

    -- carry-in = '1' for subtraction
    CT(k*(widthY+2)) <= '1';
    -- attach next dividend bit to current remainder
    RT((k+1)*(widthY+2)) <= X(k);

    -- perform subtraction using ripple-carry adder
    -- (currend partial remainder - divisor)
        bits : for i in widthY downto 0 generate  
          fa : FullAdder
	        port map (YI(i), RT((k+1)*(widthY+2)+i), CT(k*(widthY+2)+i),
		                ST(k*(widthY+1)+i), CT(k*(widthY+2)+i+1));
        end generate bits;

    -- if subtraction result is negative => quotient bit = '0'
    Q(k) <= CT(k*(widthY+2)+widthY+1);

    -- restore previous partial remainder if quotient bit = '0'
    RT(k*(widthY+2)+widthY+1 downto k*(widthY+2)+1) <=
      RT((k+1)*(widthY+2)+widthY downto (k+1)*(widthY+2))
				     when CT(k*(widthY+2)+widthY+1) = '0' else
      ST(k*(widthY+1)+widthY downto k*(widthY+1));

  end generate row;
------------------------------------------------------------------------

  -- last partial remainder is division remainder
  R <= RT(widthY downto 1);

end Structural;

-------------------------------------------------------------------------------