sintab_altera.vo

在利用Verilog在FPGA平台上输出正弦波

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

// DATE "07/06/2007 15:37:30"

// 
// Device: Altera EP2C50F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module Sintab_Altera (
	sys_clk,
	sin_output,
	counter,
	rst_n);
input 	sys_clk;
output 	[13:0] sin_output;
output 	[9:0] counter;
input 	rst_n;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("Sintab_Altera_v.sdo");
// synopsys translate_on

wire \sys_clk~combout ;
wire \sys_clk~clkctrl ;
wire \~GND ;
wire \counter[0]~90 ;
wire \rst_n~combout ;
wire \rst_n~clkctrl ;
wire \counter[0]~reg0 ;
wire \counter[0]~91 ;
wire \counter[1]~92 ;
wire \counter[1]~reg0 ;
wire \counter[1]~93 ;
wire \counter[2]~94 ;
wire \counter[2]~reg0 ;
wire \counter[2]~95 ;
wire \counter[3]~96 ;
wire \counter[3]~reg0 ;
wire \counter[3]~97 ;
wire \counter[4]~98 ;
wire \counter[4]~reg0 ;
wire \counter[4]~99 ;
wire \counter[5]~100 ;
wire \counter[5]~reg0 ;
wire \counter[5]~101 ;
wire \counter[6]~102 ;
wire \counter[6]~reg0 ;
wire \counter[6]~103 ;
wire \counter[7]~104 ;
wire \counter[7]~reg0 ;
wire \counter[7]~105 ;
wire \counter[8]~106 ;
wire \counter[8]~reg0 ;
wire \counter[8]~107 ;
wire \counter[9]~108 ;
wire \counter[9]~reg0 ;
wire \sintab1|altsyncram_component|auto_generated|q_a[0] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[1] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[2] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[3] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[4] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[5] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[6] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[7] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[8] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[9] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[10] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[11] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[12] ;
wire \sintab1|altsyncram_component|auto_generated|q_a[13] ;

wire [3:0] \sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [3:0] \sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
wire [3:0] \sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
wire [1:0] \sintab1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;

assign \sintab1|altsyncram_component|auto_generated|q_a[0]  = \sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \sintab1|altsyncram_component|auto_generated|q_a[7]  = \sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \sintab1|altsyncram_component|auto_generated|q_a[8]  = \sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \sintab1|altsyncram_component|auto_generated|q_a[9]  = \sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];

assign \sintab1|altsyncram_component|auto_generated|q_a[1]  = \sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];
assign \sintab1|altsyncram_component|auto_generated|q_a[5]  = \sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [1];
assign \sintab1|altsyncram_component|auto_generated|q_a[10]  = \sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [2];
assign \sintab1|altsyncram_component|auto_generated|q_a[13]  = \sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [3];

assign \sintab1|altsyncram_component|auto_generated|q_a[2]  = \sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];
assign \sintab1|altsyncram_component|auto_generated|q_a[3]  = \sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [1];
assign \sintab1|altsyncram_component|auto_generated|q_a[6]  = \sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [2];
assign \sintab1|altsyncram_component|auto_generated|q_a[12]  = \sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [3];

assign \sintab1|altsyncram_component|auto_generated|q_a[4]  = \sintab1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
assign \sintab1|altsyncram_component|auto_generated|q_a[11]  = \sintab1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [1];

// atom is at PIN_M1
cycloneii_io \sys_clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\sys_clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sys_clk));
// synopsys translate_off
defparam \sys_clk~I .operation_mode = "input";
defparam \sys_clk~I .input_register_mode = "none";
defparam \sys_clk~I .output_register_mode = "none";
defparam \sys_clk~I .oe_register_mode = "none";
defparam \sys_clk~I .input_async_reset = "none";
defparam \sys_clk~I .output_async_reset = "none";
defparam \sys_clk~I .oe_async_reset = "none";
defparam \sys_clk~I .input_sync_reset = "none";
defparam \sys_clk~I .output_sync_reset = "none";
defparam \sys_clk~I .oe_sync_reset = "none";
defparam \sys_clk~I .input_power_up = "low";
defparam \sys_clk~I .output_power_up = "low";
defparam \sys_clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at CLKCTRL_G3
cycloneii_clkctrl \sys_clk~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\sys_clk~combout }),
	.clkselect({gnd,gnd}),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\sys_clk~clkctrl ));
// synopsys translate_off
defparam \sys_clk~clkctrl_I .clock_type = "Global Clock";
defparam \sys_clk~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at LCCOMB_X42_Y36_N16
cycloneii_lcell_comb \~GND~I (
// Equation(s):
// \~GND  = GND

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\~GND ),
	.cout());
// synopsys translate_off
defparam \~GND~I .sum_lutc_input = "datac";
defparam \~GND~I .lut_mask = 16'h0000;
// synopsys translate_on

// atom is at LCCOMB_X42_Y34_N12
cycloneii_lcell_comb \counter[0]~90_I (
// Equation(s):
// \counter[0]~90  = \counter[0]~reg0  $ VCC
// \counter[0]~91  = CARRY(\counter[0]~reg0 )

	.dataa(\counter[0]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\counter[0]~90 ),
	.cout(\counter[0]~91 ));
// synopsys translate_off
defparam \counter[0]~90_I .sum_lutc_input = "datac";
defparam \counter[0]~90_I .lut_mask = 16'h55AA;
// synopsys translate_on

// atom is at PIN_M2
cycloneii_io \rst_n~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst_n~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(rst_n));
// synopsys translate_off
defparam \rst_n~I .operation_mode = "input";
defparam \rst_n~I .input_register_mode = "none";
defparam \rst_n~I .output_register_mode = "none";
defparam \rst_n~I .oe_register_mode = "none";
defparam \rst_n~I .input_async_reset = "none";
defparam \rst_n~I .output_async_reset = "none";
defparam \rst_n~I .oe_async_reset = "none";
defparam \rst_n~I .input_sync_reset = "none";
defparam \rst_n~I .output_sync_reset = "none";
defparam \rst_n~I .oe_sync_reset = "none";
defparam \rst_n~I .input_power_up = "low";
defparam \rst_n~I .output_power_up = "low";
defparam \rst_n~I .oe_power_up = "low";
// synopsys translate_on

// atom is at CLKCTRL_G1
cycloneii_clkctrl \rst_n~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\rst_n~combout }),
	.clkselect({gnd,gnd}),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\rst_n~clkctrl ));
// synopsys translate_off
defparam \rst_n~clkctrl_I .clock_type = "Global Clock";
defparam \rst_n~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at LCFF_X42_Y34_N13
cycloneii_lcell_ff \counter[0]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[0]~90 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[0]~reg0 ));

// atom is at LCCOMB_X42_Y34_N14
cycloneii_lcell_comb \counter[1]~92_I (
// Equation(s):
// \counter[1]~92  = \counter[1]~reg0  & !\counter[0]~91  # !\counter[1]~reg0  & (\counter[0]~91  # GND)
// \counter[1]~93  = CARRY(!\counter[0]~91  # !\counter[1]~reg0 )

	.dataa(vcc),
	.datab(\counter[1]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[0]~91 ),
	.combout(\counter[1]~92 ),
	.cout(\counter[1]~93 ));
// synopsys translate_off
defparam \counter[1]~92_I .sum_lutc_input = "cin";
defparam \counter[1]~92_I .lut_mask = 16'h3C3F;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N15
cycloneii_lcell_ff \counter[1]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[1]~92 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[1]~reg0 ));

// atom is at LCCOMB_X42_Y34_N16
cycloneii_lcell_comb \counter[2]~94_I (
// Equation(s):
// \counter[2]~94  = \counter[2]~reg0  & (\counter[1]~93  $ GND) # !\counter[2]~reg0  & !\counter[1]~93  & VCC
// \counter[2]~95  = CARRY(\counter[2]~reg0  & !\counter[1]~93 )

	.dataa(\counter[2]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[1]~93 ),
	.combout(\counter[2]~94 ),
	.cout(\counter[2]~95 ));
// synopsys translate_off
defparam \counter[2]~94_I .sum_lutc_input = "cin";
defparam \counter[2]~94_I .lut_mask = 16'hA50A;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N17
cycloneii_lcell_ff \counter[2]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[2]~94 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),