sintab_altera.v

来自「在利用Verilog在FPGA平台上输出正弦波」· Verilog 代码 · 共 24 行

module Sintab_Altera(sys_clk, sin_output,counter,rst_n);
    input sys_clk;
	 input rst_n;
    output [13:0] sin_output;	 
	 output [9:0] counter;
	 wire [13:0] sin_output;
	 
	 reg [9:0] counter;
	 
	 always @(posedge sys_clk or negedge rst_n)
	 begin
		if(~rst_n)
		begin
			counter <= 0;
		end
		else if(counter != 1024 )
			counter <= counter + 1;
		else
			counter <= 0;
	 end
	 
	 sintab sintab1(counter,sys_clk,0,0,sin_output);

endmodule