sintab_altera.tan.summary

来自「在利用Verilog在FPGA平台上输出正弦波」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.416 ns
From           : sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5]
To             : sin_output[5]
From Clock     : sys_clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'sys_clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a0~porta_address_reg9
To             : sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[0]
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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