hdlc.hif

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1588
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
mux3
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mux3.v
1183209742
7
# storage
db|hdlc.(8).cnf
db|hdlc.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mux3:mux
}
# end
# entity
flag1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
flag1.v
1183209802
7
# storage
db|hdlc.(2).cnf
db|hdlc.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
flag1:flag11
}
# end
# entity
free
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
free.v
1183210094
7
# storage
db|hdlc.(4).cnf
db|hdlc.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
free:free1
}
# end
# entity
crc1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
crc1.v
1183221892
7
# storage
db|hdlc.(3).cnf
db|hdlc.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
test501
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
test501.v
1183258596
7
# storage
db|hdlc.(5).cnf
db|hdlc.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
e0
00001
PARAMETER_BIN
DEF
e1
00010
PARAMETER_BIN
DEF
e2
00100
PARAMETER_BIN
DEF
e3
01000
PARAMETER_BIN
DEF
e4
10000
PARAMETER_BIN
DEF
}
# end
# entity
tian0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
tian0.v
1183262664
7
# storage
db|hdlc.(6).cnf
db|hdlc.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
hdlc
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
hdlc.v
1183268782
7
# storage
db|hdlc.(0).cnf
db|hdlc.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
control.v
1183301046
7
# storage
db|hdlc.(7).cnf
db|hdlc.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
control:control1
}
# end
# entity
shift32
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
shift32.v
1183301498
7
# storage
db|hdlc.(1).cnf
db|hdlc.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
d
11100011111000100101010111111001
PARAMETER_BIN
DEF
e0
00001
PARAMETER_BIN
DEF
e1
00010
PARAMETER_BIN
DEF
e2
00100
PARAMETER_BIN
DEF
e3
01000
PARAMETER_BIN
DEF
e4
10000
PARAMETER_BIN
DEF
}
# hierarchies {
shift32:shift
}
# end
# complete