time_tst.ant

来自「用VHDL写的运动计时表程序」· ANT 代码 · 共 153 行

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : ISE
//  /   /         Filename : time_tst.ant
// /___/   /\     Timestamp : Tue Oct 31 20:19:53 2006
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: time_tst
//Device: Xilinx
//
`timescale 1ns/1ps

module time_tst;
    reg clk = 1'b0;
    reg clr = 1'b0;
    reg load = 1'b0;
    reg [7:0] data_sec = 8'b01010010;
    reg [7:0] data_min = 8'b01011001;
    reg [7:0] data = 8'b00100011;
    wire [7:0] out_sec;
    wire [7:0] out_min;
    wire [7:0] out;

    parameter PERIOD = 40;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    time_going UUT (
        .clk(clk),
        .clr(clr),
        .load(load),
        .data_sec(data_sec),
        .data_min(data_min),
        .data(data),
        .out_sec(out_sec),
        .out_min(out_min),
        .out(out));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin    // Annotation process for clock clk
        #0;
        ANNOTATE_out_sec;
        ANNOTATE_out_min;
        ANNOTATE_out;
        #OFFSET;
        forever begin
            #30;
            ANNOTATE_out_sec;
            ANNOTATE_out_min;
            ANNOTATE_out;
            #10;
        end
    end

    initial begin  // Open the annotations file...
        TX_FILE = $fopen("D:\\Homework\\ISE8.1 work\\time24\\time_tst.ano");
        #4840 // Final time:  4840 ns
        $display("Success! Annotation Simulation Complete.");
        $fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
        $fclose(TX_FILE);
        $finish;
    end

    initial begin // Process for clk
    end

    initial begin // Process for Asynchronous Signals
        // -------------  Current Time:  6ns
        #6;
        clr = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  1217ns
        #1210;
        clr = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  1229ns
        #12;
        clr = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  1414ns
        #185;
        load = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  1431ns
        #16;
        load = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  2073ns
        #642;
        clr = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  2078ns
        #4;
        clr = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  3006ns
        #928;
        load = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  3011ns
        #4;
        load = 1'b0;
        // -------------------------------------
    end

    task ANNOTATE_out_sec;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,out_sec,%b]", $time, out_sec);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_out_min;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,out_min,%b]", $time, out_min);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,out,%b]", $time, out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

endmodule