time_tst.tbw

用VHDL写的运动计时表程序

version 3
D:/Homework/ISE8.1 work/time24/time_go.v
time_going
VERILOG
VERILOG
time_tst.xwv
Clocked
-
-
4800000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
20000000
20000000
10000000
10000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
data
clk
data_min
clk
data_sec
clk
out
clk
out_min
clk
out_sec
clk
clr
<ASYNC>
load
<ASYNC>
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
out_DIFF
out_min_DIFF
out_sec_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
data
data_min
data_sec
out
out_min
out_sec
clr
load
SIGNAL_ORDER_END
-X-X-X-