time24.v

来自「用VHDL写的运动计时表程序」· Verilog 代码 · 共 57 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:04:37 10/29/2006 
// Design Name: 
// Module Name:    time24 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module time24(cin, clr,load, data, out);
    input [0:0] cin;
    input [0:0] clr;
	 input [0:0] load;
    input [7:0] data;
    output [7:0] out;
	 reg [7:0] out;
	 always @(posedge cin or negedge clr or posedge load)
	  begin 
		if(load)
		  begin
		    out[7:4]<=data[7:4];
		    out[3:0]<=data[3:0];
		  end
		else if(!clr)
		  begin
		    out[7:4]<=4'd0;
		    out[3:0]<=4'd0;
		  end
		else 
		 begin
		   if(out[3:0]>=4'd9)
			  begin
			    out[3:0]<=0;
				 out[7:4]<=out[7:4]+1;
			  end
         else if((out[7:4]>=4'd2)&&(out[3:0]>=4'd3))
			  out<=0;
         else
           out<=out+1;
       end  			  
			  
	  end	


endmodule