top_sinx.hier_info

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

|top_sinx
clkin => INIT_CNT8B:U1.CLK
ain[0] => INIT_CNT8B:U1.DATA[0]
ain[1] => INIT_CNT8B:U1.DATA[1]
ain[2] => INIT_CNT8B:U1.DATA[2]
ain[3] => INIT_CNT8B:U1.DATA[3]
ain[4] => INIT_CNT8B:U1.DATA[4]
ain[5] => INIT_CNT8B:U1.DATA[5]
ain[6] => INIT_CNT8B:U1.DATA[6]
ain[7] => INIT_CNT8B:U1.DATA[7]
da_data[0] <= SINGT2:U2.DOUT[0]
da_data[1] <= SINGT2:U2.DOUT[1]
da_data[2] <= SINGT2:U2.DOUT[2]
da_data[3] <= SINGT2:U2.DOUT[3]
da_data[4] <= SINGT2:U2.DOUT[4]
da_data[5] <= SINGT2:U2.DOUT[5]
da_data[6] <= SINGT2:U2.DOUT[6]
da_data[7] <= SINGT2:U2.DOUT[7]


|top_sinx|INIT_CNT8B:U1
CLK => CNT8[6].CLK
CLK => CNT8[5].CLK
CLK => CNT8[4].CLK
CLK => CNT8[3].CLK
CLK => CNT8[2].CLK
CLK => CNT8[1].CLK
CLK => CNT8[0].CLK
CLK => COUT~reg0.CLK
CLK => CNT8[7].CLK
DATA[0] => CNT8~7.DATAB
DATA[1] => CNT8~6.DATAB
DATA[2] => CNT8~5.DATAB
DATA[3] => CNT8~4.DATAB
DATA[4] => CNT8~3.DATAB
DATA[5] => CNT8~2.DATAB
DATA[6] => CNT8~1.DATAB
DATA[7] => CNT8~0.DATAB
FOUT[0] <= CNT8[0].DB_MAX_OUTPUT_PORT_TYPE
FOUT[1] <= CNT8[1].DB_MAX_OUTPUT_PORT_TYPE
FOUT[2] <= CNT8[2].DB_MAX_OUTPUT_PORT_TYPE
FOUT[3] <= CNT8[3].DB_MAX_OUTPUT_PORT_TYPE
FOUT[4] <= CNT8[4].DB_MAX_OUTPUT_PORT_TYPE
FOUT[5] <= CNT8[5].DB_MAX_OUTPUT_PORT_TYPE
FOUT[6] <= CNT8[6].DB_MAX_OUTPUT_PORT_TYPE
FOUT[7] <= CNT8[7].DB_MAX_OUTPUT_PORT_TYPE
COUT <= COUT~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top_sinx|SINGT2:U2
CLK => Q[5].CLK
CLK => Q[4].CLK
CLK => Q[3].CLK
CLK => Q[2].CLK
CLK => Q[1].CLK
CLK => Q[0].CLK
CLK => data_rom_10k:u1.inclock
CLK => Q[6].CLK
DOUT[0] <= data_rom_10k:u1.q[0]
DOUT[1] <= data_rom_10k:u1.q[1]
DOUT[2] <= data_rom_10k:u1.q[2]
DOUT[3] <= data_rom_10k:u1.q[3]
DOUT[4] <= data_rom_10k:u1.q[4]
DOUT[5] <= data_rom_10k:u1.q[5]
DOUT[6] <= data_rom_10k:u1.q[6]
DOUT[7] <= data_rom_10k:u1.q[7]


|top_sinx|SINGT2:U2|data_rom_10k:u1
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
inclock => lpm_rom:lpm_rom_component.inclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]


|top_sinx|SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE


|top_sinx|SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT