trans4to8.vhd

来自「用VHDL语言实现数显时钟」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;

Entity trans4to8 is
port(in4:in std_logic_vector(3 downto 0);
	out8:out std_logic_vector(7 downto 0)
);
end trans4to8;

architecture art of trans4to8 is
begin
	with in4 select
out8<= "11111100" when "0000",
	  "01100000" when "0001",
	  "11011010" when "0010",
	  "11110010" when "0011",
	  "01100110" when "0100",
	  "10110110" when "0101",
	  "10111110" when "0110",
	  "11100100" when "0111",
	  "11111110" when "1000",
	  "11110110" when "1001",
	  "11101110" when "1010",
	  "00111110" when "1011",
	  "10011110" when "1100",
	  "01111010" when "1101",
	  "10011110" when "1110",
	  "10001110" when "1111",
	  "00000001" when others;
end art;