mux61.vhd

来自「用VHDL语言实现数显时钟」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity mux61 is
port(Choose:in std_logic_vector(2 downto 0);
	 HHour:in std_logic_vector(3 downto  0);
	 LHour:in std_logic_vector(3 downto 0);
	 HMinute:in std_logic_vector(3 downto 0);
	 LMinute:in std_logic_vector(3 downto 0);
	 HSencond:in std_logic_vector(3 downto 0);
	 LSencond:in std_logic_vector(3 downto 0);
	 TimeOut:out std_logic_vector(3 downto 0)
);
end mux61;

architecture art of mux61 is
begin
with Choose select
TimeOut<=HHour when "111" ,
		  LHour when "110",
		  HMinute when "100",
		  LMinute when "011",
		  HSencond when "001",
		  LSencond when "000",
          "0000" when others;

end art;