devid200.vhd

用VHDL语言实现数显时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity devid200 is
port(clkin:in std_logic;
	 arst:in std_logic;
	 clkout:out std_logic
);
end devid200;

architecture art of devid200 is
signal counter:std_logic_vector(17 downto 0);
signal clkflag:std_logic;

begin
clkout<=clkflag;
process(clkin,arst)
begin
if arst='1' then
		counter<="000000000000000000";
		clkflag<='0';
elsif (clkin'event and clkin='1') then
	if counter="000000000000000100" then --=0100实际是10个周期产生一个周期
		counter<="000000000000000000";
		clkflag<=not clkflag;
	else counter<=counter+'1';	
	end if;
	end if;
end process;
end art;