timecount.vhd

用VHDL语言实现数显时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity timecount is
port(clk:in std_logic;
	 arst:in std_logic;
     HHour:out std_logic_vector(3 downto 0);
 	 LHour:out std_logic_vector(3 downto 0); 
	 HMinute:out std_logic_vector(3 downto 0);
	 LMinute:out std_logic_vector(3 downto 0);
	 HSecond:out std_logic_vector(3 downto 0);
	 LSecond:out std_logic_vector(3 downto 0)
);
end timecount;

architecture art of timecount is
signal hour:std_logic_vector(7 downto 0);
signal minute:std_logic_vector(7 downto 0);
signal second:std_logic_vector(7 downto 0);
signal sflag:std_logic;
signal mflag:std_logic;
begin
LSecond<=second(3 downto 0);
HSecond<=second(7 downto 4);
LMinute<=minute(3 downto 0);
HMinute<=minute(7 downto 4);
LHour<=hour(3 downto 0);
HHour<=hour(7 downto 4);

process(clk,arst)
begin
if arst='1'  then 
 	second<="00000000";
	sflag<='0';
elsif clk'event and clk='1' then 
	if second(3 downto 0)="1001" then 
	second(3 downto 0)<="0000";
			if second(7 downto 4)="0101" then
				second<="00000000";
				sflag<='1';
			else
			second(7 downto 4)<=second(7 downto 4)+1;
			end if; 
	else
	second(3 downto 0)<=second(3 downto 0)+1;
	sflag<='0';
    end if ;
end if;
end process;

process(sflag,arst)
begin
if arst='1'  then 
 	minute<="00000000";
	mflag<='0';
elsif sflag'event and sflag='1' then 
	if minute(3 downto 0)="1001" then 
	minute(3 downto 0)<="0000";
			if minute(7 downto 4)="0101" then
				minute<="00000000";
				mflag<='1';
			else
			minute(7 downto 4)<=minute(7 downto 4)+1;
			end if; 
	else
	minute(3 downto 0)<=minute(3 downto 0)+1;
	mflag<='0';
    end if ;
end if;
end process;

process(mflag,arst)
begin
if arst='1' then 
	hour<="00000000";
elsif mflag'event and mflag='1' then
	if hour(3 downto 0)="0011" then 
		hour(3 downto 0)<="0000";
			if hour(7 downto 4)="0010" then
				hour<="00000000";
			else 
				hour(7 downto 4)<=hour(7 downto 4)+1;
			end if;
	else
		hour(3 downto 0)<=hour(3 downto 0)+1;	
	end if ;
end if;
end process;

end art;