scan.vhd

用VHDL语言实现数显时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity scan is
port(clk:in std_logic;
	 arst:in std_logic;
	 outscan:out std_logic_vector(2 downto 0)
);
end scan;

architecture art of scan is
signal scan1s:std_logic_vector(2 downto 0);
signal scan2s:std_logic_vector(2 downto 0);
begin
outscan<=scan2s;

process(clk,arst)
begin
if arst='1' then
	scan1s<="000";
elsif clk'event and clk='1' then
	if scan1s="101" then
		scan1s<="000";
	else 
		scan1s<=scan1s+'1';
	end if;
end if;
end process;

with scan1s select
	 scan2s<="000" when"000",
	  		 "001" when"001",
	  		 "011" when"010",
	  		 "100" when"011",
	  		 "110" when"100",
	  		 "111" when others;

end art;