test.vhd

用VHDL语言实现数显时钟

library ieee;
use ieee.std_logic_1164.all;

entity test is
port(sin:in std_logic_vector(3 downto 0);
	 a,b,c,d:out std_logic);
end test;

architecture arch of test is
--signal cin:std_logic_vector(3 downto 0); 
begin
a<=sin(0);
b<=sin(1);
c<=sin(2);
d<=sin(3);
end arch;