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Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledERROR:HDLCompilers:26 - clkgen.v line 8 expecting 'endmodule', found 'module'ERROR:HDLCompilers:26 - clkgen.v line 46 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'din' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'q' was not declared as input, inout or outputModule <dff> compiledERROR:HDLCompilers:26 - clkgen.v line 54 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk1' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'din' was not declared as input, inout or outputModule <dff1> compiledERROR:HDLCompilers:26 - clkgen.v line 77 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk4' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'din' was not declared as input, inout or outputModule <dff4> compiledERROR:HDLCompilers:26 - clkgen.v line 84 expecting 'EOF', found 'and'Analysis of file <clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledERROR:HDLCompilers:26 - clkgen.v line 8 expecting 'endmodule', found 'module'ERROR:HDLCompilers:26 - clkgen.v line 46 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'din' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'q' was not declared as input, inout or outputModule <dff> compiledERROR:HDLCompilers:26 - clkgen.v line 54 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk1' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'din' was not declared as input, inout or outputModule <dff1> compiledERROR:HDLCompilers:26 - clkgen.v line 77 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk4' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'din' was not declared as input, inout or outputModule <dff4> compiledERROR:HDLCompilers:26 - clkgen.v line 84 expecting 'EOF', found 'and'Analysis of file <clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledERROR:HDLCompilers:26 - clkgen.v line 8 expecting 'endmodule', found 'module'ERROR:HDLCompilers:26 - clkgen.v line 46 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'din' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'q' was not declared as input, inout or outputModule <dff> compiledERROR:HDLCompilers:26 - clkgen.v line 54 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk1' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'din' was not declared as input, inout or outputModule <dff1> compiledERROR:HDLCompilers:26 - clkgen.v line 77 expecting ';', found 'input'ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk4' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk' was not declared as input, inout or outputERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'din' was not declared as input, inout or outputModule <dff4> compiledERROR:HDLCompilers:26 - clkgen.v line 84 expecting 'EOF', found 'and'Analysis of file <fsm_clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clkgen>.Module <clkgen> is correct for synthesis. Set property "resynthesize = true" for unit <clkgen>.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clkgen>. Related source file is clkgen.v. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 5 | | Inputs | 0 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | 00001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <clk1>. Found 1-bit register for signal <clk2>. Found 1-bit register for signal <clk3>. Found 1-bit register for signal <clk4>. Summary: inferred 1 Finite State Machine(s). inferred 4 D-type flip-flop(s).Unit <clkgen> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Registers : 9 1-bit register : 9==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clkgen> ...Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200eft256-7 Number of Slices: 8 out of 2352 0% Number of Slice Flip Flops: 9 out of 4704 0% Number of 4 input LUTs: 3 out of 4704 0% Number of bonded IOBs: 5 out of 182 2% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -7 Minimum period: 4.992ns (Maximum Frequency: 200.321MHz) Minimum input arrival time before clock: 4.466ns Maximum output required time after clock: 6.140ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clkgen>.Module <clkgen> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clkgen>. Related source file is clkgen.v. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 5 | | Inputs | 0 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | 00001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <clk1>. Found 1-bit register for signal <clk2>. Found 1-bit register for signal <clk3>. Found 1-bit register for signal <clk4>. Summary: inferred 1 Finite State Machine(s). inferred 4 D-type flip-flop(s).Unit <clkgen> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Registers : 9 1-bit register : 9==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clkgen> ...Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200eft256-7 Number of Slices: 8 out of 2352 0% Number of Slice Flip Flops: 9 out of 4704 0% Number of 4 input LUTs: 3 out of 4704 0% Number of bonded IOBs: 5 out of 182 2% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -7 Minimum period: 4.992ns (Maximum Frequency: 200.321MHz) Minimum input arrival time before clock: 4.466ns Maximum output required time after clock: 6.140ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
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