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verilog 编写的pic16c5x时钟模块

=========================================================================
Completed process "Synthesize".



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Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_5.7c/tcl/vsim/pref.tcl 

# 5.7c

# do wave.ado 
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module clkgen
# 
# Top level modules:
# 	clkgen
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module wave
# 
# Top level modules:
# 	wave
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps wave glbl 
# Loading work.wave
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "E:\fpga\XilinxCoreLib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "E:\fpga\unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.clkgen
# ** Warning: (vsim-3009) [TSCALE] - Module 'clkgen' does not have a `timescale directive in effect, but previous modules do.
#         Region: /wave/UUT
# Loading work.glbl
# Success! Annotation Simulation Complete.
# Break at wave.ant line 61
# Stopped at wave.ant line 61 


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Project Navigator Auto-Make Log File
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Launching Application for process "Generate Expected Simulation Results".

Reading C:/Modeltech_5.7c/tcl/vsim/pref.tcl 

# 5.7c

# do wave.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module clkgen
# 
# Top level modules:
# 	clkgen
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module wave
# 
# Top level modules:
# 	wave
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps wave glbl 
# Loading work.wave
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "E:\fpga\XilinxCoreLib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "E:\fpga\unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.clkgen
# ** Warning: (vsim-3009) [TSCALE] - Module 'clkgen' does not have a `timescale directive in effect, but previous modules do.
#         Region: /wave/UUT
# Loading work.glbl
# Success! Annotation Simulation Complete.
# Break at wave.ant line 61
# Stopped at wave.ant line 61 


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
No errors in compilation
Analysis of file <clkgen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clkgen>.
Module <clkgen> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <clkgen>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clkgen>.
    Related source file is clkgen.v.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 4-bit latch for signal <out>.
    Summary:
	inferred   1 Finite State Machine(s).
Unit <clkgen> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 5
 1-bit register                    : 5
# Latches                          : 1
 4-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clkgen> ...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200eft256-7 

 Number of Slices:                       5  out of   2352     0%  
 Number of Slice Flip Flops:             9  out of   4704     0%  
 Number of 4 input LUTs:                 3  out of   4704     0%  
 Number of bonded IOBs:                  5  out of    182     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0005(_n00051:O)                  | NONE(*)(out_0)         | 4     |
clk                                | BUFGP                  | 5     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 3.140ns (Maximum Frequency: 318.471MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.229ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



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Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
No errors in compilation
Analysis of file <clkgen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clkgen>.
Module <clkgen> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clkgen>.
    Related source file is clkgen.v.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 4-bit latch for signal <out>.
    Summary:
	inferred   1 Finite State Machine(s).
Unit <clkgen> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 5
 1-bit register                    : 5
# Latches                          : 1
 4-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
No errors in compilation
Analysis of file <clkgen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:188 - clkgen.v line 46 Index in bit-select of vector reg 'D' is out of range
Analyzing top module <clkgen>.
ERROR:Xst:868 - clkgen.v line 46: Index out of range for D.
    Set property "resynthesize = true" for unit <clkgen>.
 
Found 1 error(s). Aborting synthesis.
--> 

Total memory usage is 48276 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
No errors in compilation
Analysis of file <clkgen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clkgen>.
ERROR:Xst:855 - clkgen.v line 39: Unsupported procedural assignment for signal <D>.
    Set property "resynthesize = true" for unit <clkgen>.
 
Found 1 error(s). Aborting synthesis.
--> 

Total memory usage is 48276 kilobytes