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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"ERROR:HDLCompilers:26 - clkgen.v line 9 unexpected token: '='ERROR:HDLCompilers:26 - clkgen.v line 14 unexpected token: 'posedge'ERROR:HDLCompilers:26 - clkgen.v line 15 expecting ';', found 'begin'Module <clkgen> compiledERROR:HDLCompilers:26 - clkgen.v line 16 expecting 'endmodule', found 'if'Analysis of file <clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"ERROR:HDLCompilers:26 - clkgen.v line 14 unexpected token: 'reset'ERROR:HDLCompilers:26 - clkgen.v line 34 expecting 'endcase', found 'end'ERROR:HDLCompilers:26 - clkgen.v line 35 expecting 'end', found 'endmodule'Module <clkgen> compiledERROR:HDLCompilers:26 - clkgen.v line 36 expecting 'endmodule', found 'EOF'Analysis of file <clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"ERROR:HDLCompilers:26 - clkgen.v line 14 unexpected token: 'reset'Module <clkgen> compiledAnalysis of file <clkgen.prj> failed.--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================ERROR:HDLCompilers:247 - clkgen.v line 30 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 30 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 31 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 31 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 32 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 32 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 33 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 33 Illegal left hand side of blocking assignment--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================ERROR:HDLCompilers:247 - clkgen.v line 30 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 30 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 31 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 31 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 32 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 32 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - clkgen.v line 33 Reference to vector wire 'out' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - clkgen.v line 33 Illegal left hand side of blocking assignment--> Total memory usage is 48276 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clkgen>.WARNING:Xst:883 - clkgen.v line 21: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 22: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 23: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 24: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 31: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 32: Ignored duplicate item in case statement. WARNING:Xst:883 - clkgen.v line 33: Ignored duplicate item in case statement. Module <clkgen> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================INFO:Xst:1304 - Contents of register <state> in unit <clkgen> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <out> in unit <clkgen> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <clkgen>. Related source file is clkgen.v.Unit <clkgen> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clkgen> ...Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200eft256-7 Number of bonded IOBs: 3 out of 182 1% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -7 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "clkgen.v"Module <clkgen> compiledNo errors in compilationAnalysis of file <clkgen.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <clkgen>.Module <clkgen> is correct for synthesis. Set property "resynthesize = true" for unit <clkgen>.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clkgen>. Related source file is clkgen.v. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 5 | | Inputs | 0 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | reset (negative) | | Reset type | asynchronous | | Reset State | 00001 | | Encoding | automatic | | Implementation | LUT | -----------------------------------------------------------------------WARNING:Xst:737 - Found 4-bit latch for signal <out>. Summary: inferred 1 Finite State Machine(s).Unit <clkgen> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Registers : 5 1-bit register : 5# Latches : 1 4-bit latch : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clkgen> ...Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200eft256-7 Number of Slices: 5 out of 2352 0% Number of Slice Flip Flops: 9 out of 4704 0% Number of 4 input LUTs: 3 out of 4704 0% Number of bonded IOBs: 5 out of 182 2% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+_n0005(_n00051:O) | NONE(*)(out_0) | 4 |clk | BUFGP | 5 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -7 Minimum period: 3.140ns (Maximum Frequency: 318.471MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.229ns Maximum combinational path delay: No path found⌨️ 快捷键说明
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