clkgen.gfl

verilog 编写的pic16c5x时钟模块

# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# View RTL Schematic
clkgen.ngr
# ProjNav -> New Source -> TBW
e:\fpga\clkgen\__projnav\hb_cmds
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# View RTL Schematic
clkgen.ngr
# ProjNav -> New Source -> TBW
e:\fpga\clkgen\__projnav\hb_cmds
# ProjNav -> New Source -> TBW
e:\fpga\clkgen\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
wave.ado
wave.ano
# ModelSim : Generate Expected Simulation Results
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
wave.ado
wave.ano
# ModelSim : Generate Expected Simulation Results
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# View RTL Schematic
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# ProjNav -> New Source -> TBW
E:\fpga\clkgen\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Launch ModelSim Simulator
clkgen.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ProjNav -> New Source -> TBW
E:\fpga\clkgen\__projnav\hb_cmds
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# View RTL Schematic
clkgen.ngr
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Generate Expected Simulation Results
wave.ado
wave.ano
# ModelSim : Generate Expected Simulation Results
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
wave.ado
wave.ano
# ModelSim : Generate Expected Simulation Results
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
dff.lso
# xst flow : RunXST
dff.syr
dff.prj
dff.sprj
dff.ana
dff.stx
dff.cmd_log
# XST (Creating Lso File) : 
dff.lso
# xst flow : RunXST
dff.syr
dff.prj
dff.sprj
dff.ana
dff.stx
dff.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
fsm_clkgen.lso
# xst flow : RunXST
fsm_clkgen.syr
fsm_clkgen.prj
fsm_clkgen.sprj
fsm_clkgen.ana
fsm_clkgen.stx
fsm_clkgen.cmd_log
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# XST (Creating Lso File) : 
clkgen.lso
# xst flow : RunXST
clkgen.syr
clkgen.prj
clkgen.sprj
clkgen.ana
clkgen.stx
clkgen.cmd_log
clkgen.ngc
clkgen.ngr
# ProjNav -> New Source -> TBW
E:\fpga\clkgen\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wave.vhw
wave.ano
wave.tfw
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)