wave.tfw

verilog 编写的pic16c5x时钟模块

// E:\FPGA\CLKGEN
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Fri May 18 22:21:23 2007
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module wave;
	reg clk;
	reg reset;
	wire clk1;
	wire clk2;
	wire clk3;
	wire clk4;

	defparam UUT.idle = 0;
	defparam UUT.q1 = 1;
	defparam UUT.q2 = 2;
	defparam UUT.q3 = 3;
	defparam UUT.q4 = 4;

	clkgen UUT (
		.clk(clk),
		.reset(reset),
		.clk1(clk1),
		.clk2(clk2),
		.clk3(clk3),
		.clk4(clk4)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#10
	clk = 1'b1;
	#10
	#40
	clk = 1'b0;
	#40
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	reset = 1'b0;
	// --------------------
	#100 // Time=100 ns
	reset = 1'b0;
	// --------------------
	#700 // Time=800 ns
	reset = 1'b0;
	// --------------------
	#400 // Time=1200 ns
	reset = 1'b1;
	// --------------------
	#4500 // Time=5700 ns
	reset = 1'b1;
	// --------------------
	#100 // Time=5800 ns
	reset = 1'b1;
	// --------------------
	#100 // Time=5900 ns
	reset = 1'b1;
	// --------------------
	#510 // Time=6410 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_clk1;
	input NEXT_clk1;

	#0 begin
		if (NEXT_clk1 !== clk1) begin
			$display("Error at time=%dns clk1=%b, expected=%b",
				$time, clk1, NEXT_clk1);
			$fdisplay(TX_FILE,"Error at time=%dns clk1=%b, expected=%b",
				$time, clk1, NEXT_clk1);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_clk2;
	input NEXT_clk2;

	#0 begin
		if (NEXT_clk2 !== clk2) begin
			$display("Error at time=%dns clk2=%b, expected=%b",
				$time, clk2, NEXT_clk2);
			$fdisplay(TX_FILE,"Error at time=%dns clk2=%b, expected=%b",
				$time, clk2, NEXT_clk2);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_clk3;
	input NEXT_clk3;

	#0 begin
		if (NEXT_clk3 !== clk3) begin
			$display("Error at time=%dns clk3=%b, expected=%b",
				$time, clk3, NEXT_clk3);
			$fdisplay(TX_FILE,"Error at time=%dns clk3=%b, expected=%b",
				$time, clk3, NEXT_clk3);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_clk4;
	input NEXT_clk4;

	#0 begin
		if (NEXT_clk4 !== clk4) begin
			$display("Error at time=%dns clk4=%b, expected=%b",
				$time, clk4, NEXT_clk4);
			$fdisplay(TX_FILE,"Error at time=%dns clk4=%b, expected=%b",
				$time, clk4, NEXT_clk4);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule