wave.fdo

verilog 编写的pic16c5x时钟模块

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri May 18 22:21:29 中国标准时间 2007
##
vlib work
vlog  clkgen.v
vlog  wave.tfw
vlog  "C:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work wave glbl
do wave.udo
view wave
add wave *
view structure
view signals
run -all