square_number_inst.tdf

Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A c

(
	result_sig[]
) = square_number	(
	.clock0 = clock0_sig,
	.dataa_0[] = dataa_0_sig[],
	.dataa_1[] = dataa_1_sig[],
	.datab_0[] = datab_0_sig[],
	.datab_1[] = datab_1_sig[]
)
RETURNS (
	.result[]
);