root_pipeline_wrapper.tdf

来自「Verilog HDL: Magnitude For a vector (a,」· TDF 代码 · 共 49 行

--*********************************************************************
--*** TOP_LEVEL_ROOTB												***
--***																***
--*** Parameterized Square Root Function							***
--***																***
--*** Usage:														***
--***																***
--*** WIDTH : Input Word Precision - any value > 6					***
--*** PREC : Output Word Precision - any value > (WIDTH/2)			***
--***																***
--*** (WIDTH/2) most significant bits of output contain the root,	***
--*** following bits are the fractional portion of the root			***
--***																***
--*** Compile with Carry Chains										***
--***																***
--***																***
--***																***
--*********************************************************************

FUNCTION roota_opt_pipeline (rad[WIDTH..1], clk, clken, aclr)
	RETURNS (root[PREC..1]);


PARAMETERS
(
 WIDTH = 20,
 PREC = 15,
 PIPELINE = "YES"
);

subdesign root_pipeline_wrapper
(
 rad[WIDTH..1] : INPUT;
 clk		   : INPUT;
 clken		   : INPUT;
 aclr		   : INPUT;
 root[PREC..1] : OUTPUT;
)

BEGIN

  root[] = roota_opt_pipeline (rad[], clk, clken, aclr) WITH (WIDTH=WIDTH,PREC=PREC,PIPELIBE=PIPELINE);

END;