fpq1s.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fpq1S is
      Port (CLK:in std_logic;
	       CP:out std_logic);
end fpq1S;

architecture Behavioral of fpq1S is
  signal count:integer range 0 to 50000000;
    begin
	process(CLK)
		begin
		  if(CLK'event and CLK='1') then
		          if count=49999999 then
			         count<=0;
				else
				    count<=count+1;
				end if;
			 case count is
			   when 0         to 24999999=>CP<='1';
			   when 25000000  to 49999999=>CP<='0';
			   when others =>CP<='Z';
			 end case;
		  end if;
	end process;
end Behavioral;