bskz.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 39 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bskz is
  port(mshi,mge,sshi,sge:in std_logic_vector(3 downto 0);
       clk:in std_logic;
	  cp500: buffer std_logic:='1';
	  cp1000:buffer std_logic:='1'); 
end bskz;

architecture Behavioral of bskz is

begin
   process(clk)
   begin
      if clk'event and clk='1' then
	   if mshi="0101" and mge="1001" and sshi="0101" then
	      if sge="0000" or sge="0010" or sge="0100" or sge="0110" or sge="1000" then
		    cp500<='0';
		 else
		    cp500<='1';
		 end if;
	   end if;
	   if mshi="0000" and mge="0000" and sshi="0000" and sge="0000" then
	         cp1000<='0';
	   else
	         cp1000<='1';
	   end if;
	 end if;
   end process;
end Behavioral;