fen_sound.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 41 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fpq_sound is
      Port (CLK:in std_logic;
	       CP500,CP1000:out std_logic);
end fpq_sound;

architecture Behavioral of fpq_sound is
  signal count:integer range 0 to 50000;
  signal x:std_logic;
  signal y:std_logic;
    begin
	process(CLK)
     begin
	   if(CLK'event and CLK='1') then
		     if count=50000 then
			   count<=0;
		        x<=not x;
		     else
			   count<=count+1;
		     end if;
		  end if;	  
	end process;
	   CP1000<=x;
     process(x)
	begin 
	   if x'event and x='1' then
	      y<=not y;
	   end if;
	   CP500<=y;
     end process;	      	   
end Behavioral;