xzq6.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 41 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SZQ is
    Port ( Q1 : in std_logic_vector(3 downto 0);
           Q2 : in std_logic_vector(3 downto 0);
           Q3 : in std_logic_vector(3 downto 0);
           Q4 : in std_logic_vector(3 downto 0);
		 Q5 : in std_logic_vector(3 downto 0);
           Q6 : in std_logic_vector(3 downto 0);
            S : in std_logic_vector(2 downto 0);
           Q : out std_logic_vector(3 downto 0));
end SZQ;

architecture Behavioral of SZQ is
begin
  process(S)
  begin
	if S="000" then 
	   Q<=Q6;
	 elsif S="001" then 
	   Q<=Q5;
	 elsif S="010" then 
	   Q<=Q4;
	 elsif S="011" then 
	   Q<=Q3;
	 elsif S="100" then 
	   Q<=Q2;
	 else
	   Q<=Q1;
	 end if;
  end process;
end Behavioral;