hdpdeps.ref

来自「数字钟的实现」· REF 代码 · 共 170 行

V3 133
FL E:/VHDL/dig_clk/clock.vhf 2007/03/16.11:24:02 I.24
FL e:/vhdl/dig_clk/S_6.vhdl 2007/03/16.09:49:18 I.24
FL E:/VHDL/dig_clk/HOUR.vhdl 2007/03/16.09:41:28 I.24
EN work/char 0            FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/lcd_val.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
FL E:/VHDL/waitpast/dig_clk/xzq6.vhdl 2007/03/16.10:20:10 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl 2007/05/16.17:20:26 I.24
EN work/MIN 1179308663             FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/MIN/BEHAVIORAL 1179308664  FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl EN work/MIN 1179308663
FL E:/VHDL/dig_clk/SECOND1.vhdl 2007/03/16.11:02:32 I.24
FL E:/VHDL/waitpast/dig_clk/YMQ.vhdl 2007/03/16.22:48:08 I.24
EN work/YMQ 0             FL E:/VHDL/waitpast/dig_clk/YMQ.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/YMQ/BEHAVIORAL 0  FL E:/VHDL/waitpast/dig_clk/YMQ.vhdl EN work/YMQ 0
FL E:/VHDL/waitpast/dig_clk/s59.vhdl 2007/04/18.09:25:06 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd 2007/05/16.17:43:22 I.24
EN work/LCD1602 1179308669         FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/LCD1602/Behavioral 1179308670 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd \
      EN work/LCD1602 1179308669
FL E:/VHDL/dig_clk/S_6.vhdl 2007/03/16.09:49:18 I.24
FL E:/VHDL/past/dig_clk/ch_bcd_integer.vhdl 2007/04/17.19:22:12 I.24
FL D:/waitpast/dig_clk/sel6.vhdl 2007/03/16.17:01:34 I.24
EN work/SEL6 0            FL D:/waitpast/dig_clk/sel6.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SEL6/BEHAVIORAL 0 FL D:/waitpast/dig_clk/sel6.vhdl EN work/SEL6 0
FL E:/VHDL/waitpast/dig_clk/clock.vhf 2007/03/18.09:15:12 I.24
EN work/CLOCK 0           FL E:/VHDL/waitpast/dig_clk/clock.vhf \
      PB ieee/std_logic_1164 1131108373 PH ieee/NUMERIC_STD 1131108384
AR work/CLOCK/BEHAVIORAL 0 FL E:/VHDL/waitpast/dig_clk/clock.vhf EN work/CLOCK 0 \
      CP BSKZ           CP FPQ_SOUND      CP FPQ1S          CP FPQ2MS         CP HOUR \
      CP MIN            CP SZQ            CP OR2            CP INV            CP AND2 \
      CP SEL6           CP YIMAQI         CP MIAO
FL E:/VHDL/past/dig_clk/HOUR.vhdl 2007/03/16.09:41:28 I.24
FL E:/VHDL/past/dig_clk/digclk.vhf 2007/04/17.20:25:54 I.24
FL E:/VHDL/waitpast/dig_clk/fpq4mhz.vhdl 2007/04/18.08:44:38 I.24
EN work/FP4MHZ 0          FL E:/VHDL/waitpast/dig_clk/fpq4mhz.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/FP4MHZ/BEHAVIORAL 0 FL E:/VHDL/waitpast/dig_clk/fpq4mhz.vhdl EN work/FP4MHZ 0
FL e:/vhdl/dig_clk/FPQ1S.vhdl 2007/03/16.09:42:38 I.24
FL E:/VHDL/past/dig_clk/lcd.vhdl 2007/04/17.20:18:40 I.24
FL D:/waitpast/dig_clk/FPQ2MS.vhdl 2007/03/16.09:43:14 I.24
EN work/FPQ2MS 0          FL D:/waitpast/dig_clk/FPQ2MS.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/FPQ2MS/BEHAVIORAL 0 FL D:/waitpast/dig_clk/FPQ2MS.vhdl EN work/FPQ2MS 0
FL e:/vhdl/dig_clk/SEL.vhdl 2007/03/16.09:43:30 I.24
EN work/SEL 0             FL e:/vhdl/dig_clk/SEL.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SEL/BEHAVIORAL 0  FL e:/vhdl/dig_clk/SEL.vhdl EN work/SEL 0
FL e:/vhdl/waitpast/dig_clk/miao.vhdl 2007/03/20.11:13:58 I.24
EN work/MIAO 0            FL e:/vhdl/waitpast/dig_clk/miao.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/MIAO/BEHAVIORAL 0 FL e:/vhdl/waitpast/dig_clk/miao.vhdl EN work/MIAO 0
FL E:/VHDL/dig_clk/FPQ1S.vhdl 2007/03/16.09:42:38 I.24
FL E:/VHDL/dig_clk/bskz.vhdl 2007/03/16.10:11:30 I.24
FL E:/VHDL/past/dig_clk/FEN_SOUND.vhdl 2007/03/16.10:02:50 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl 2007/05/16.16:57:38 I.24
EN work/FPQ_SOUND 1179308659       FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/FPQ_SOUND/BEHAVIORAL 1179308660 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl \
      EN work/FPQ_SOUND 1179308659
FL E:/VHDL/waitpast/dig_clk/S_6.vhdl 2007/03/16.16:59:44 I.24
EN work/S_6 0             FL E:/VHDL/waitpast/dig_clk/S_6.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/S_6/BEHAVIORAL 0  FL E:/VHDL/waitpast/dig_clk/S_6.vhdl EN work/S_6 0
FL e:/vhdl/dig_clk/xzq6.vhdl 2007/03/16.10:20:10 I.24
FL D:/waitpast/dig_clk/xzq6.vhdl 2007/03/16.10:20:10 I.24
EN work/SZQ 0             FL D:/waitpast/dig_clk/xzq6.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SZQ/BEHAVIORAL 0  FL D:/waitpast/dig_clk/xzq6.vhdl EN work/SZQ 0
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf 2007/05/16.17:44:08 I.24
EN work/DIGCLK 1179308671          FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf \
      PB ieee/std_logic_1164 1131108373 PH ieee/NUMERIC_STD 1131108384
AR work/DIGCLK/BEHAVIORAL 1179308672 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf \
      EN work/DIGCLK 1179308671 CP BSKZ    CP FPQ_SOUND      CP FPQ1S          CP MIN \
      CP HOUR           CP S59            CP OR2            CP AND2           CP LCD1602
FL D:/waitpast/dig_clk/s59.vhdl 2007/03/20.11:15:28 I.24
FL D:/waitpast/dig_clk/yimaqi.vhdl 2007/03/18.08:28:42 I.24
EN work/YIMAQI 0          FL D:/waitpast/dig_clk/yimaqi.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/YIMAQI/BEHAVIORAL 0 FL D:/waitpast/dig_clk/yimaqi.vhdl EN work/YIMAQI 0
FL E:/VHDL/past/dig_clk/s59.vhdl 2007/03/20.11:15:28 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl 2007/05/16.17:21:16 I.24
EN work/HOUR 1179308665            FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/HOUR/BEHAVIORAL 1179308666 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl \
      EN work/HOUR 1179308665
FL D:/waitpast/dig_clk/digclk.vhf 2007/03/20.11:30:18 I.24
FL E:/VHDL/waitpast/dig_clk/ch_bcd_integer.vhdl 2007/04/18.11:09:44 I.24
EN work/CH_BCD_INTEGER 0  FL E:/VHDL/waitpast/dig_clk/ch_bcd_integer.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/CH_BCD_INTEGER/BEHAVIORAL 0 FL E:/VHDL/waitpast/dig_clk/ch_bcd_integer.vhdl \
      EN work/CH_BCD_INTEGER 0
FL e:/vhdl/past/dig_clk/lcd.vhdl 2007/04/17.20:18:40 I.24
FL E:/VHDL/waitpast/dig_clk/miao.vhdl 2007/03/18.08:33:48 I.24
FL D:/waitpast/dig_clk/MIN.vhdl 2007/03/20.11:26:54 I.24
FL E:/VHDL/past/dig_clk/MIN.vhdl 2007/03/20.11:26:54 I.24
FL e:/vhdl/dig_clk/clock.vhf 2007/03/16.10:42:38 I.24
FL e:/vhdl/dig_clk/HOUR.vhdl 2007/03/16.09:41:28 I.24
FL E:/VHDL/past/dig_clk/bskz.vhdl 2007/03/16.10:11:30 I.24
FL D:/waitpast/dig_clk/HOUR.vhdl 2007/03/16.09:41:28 I.24
FL E:/VHDL/dig_clk/second.vhdl 2007/03/16.10:59:22 I.24
EN work/SECOND 0          FL E:/VHDL/dig_clk/second.vhdl PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SECOND/BEHAVIORAL 0 FL E:/VHDL/dig_clk/second.vhdl EN work/SECOND 0
FL D:/waitpast/dig_clk/FEN_SOUND.vhdl 2007/03/16.10:02:50 I.24
FL e:/vhdl/dig_clk/second.vhdl 2007/03/16.09:36:28 I.24
FL E:/VHDL/dig_clk/FPQ2MS.vhdl 2007/03/16.09:43:14 I.24
FL E:/VHDL/past/dig_clk/FPQ1S.vhdl 2007/03/16.09:42:38 I.24
FL e:/vhdl/dig_clk/FPQ2MS.vhdl 2007/03/16.09:43:14 I.24
FL E:/VHDL/waitpast/dig_clk/SECOND1.vhdl 2007/03/18.08:31:12 I.24
EN work/SEC 0             FL E:/VHDL/waitpast/dig_clk/SECOND1.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SEC/BEHAVIORAL 0  FL E:/VHDL/waitpast/dig_clk/SECOND1.vhdl EN work/SEC 0
FL e:/vhdl/dig_clk/YMQ.vhdl 2007/03/16.09:50:00 I.24
FL e:/vhdl/dig_clk/MIN.vhdl 2007/03/16.09:33:38 I.24
EN work/CHAR_RAM 0        FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/lcd.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/CHAR_RAM/FUN 0    FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/lcd.vhdl \
      EN work/CHAR_RAM 0
EN work/LCD 0             FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/lcd.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/LCD/BEHAVIORAL 0  FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/lcd.vhdl EN work/LCD 0 \
      CP CHAR_RAM
FL E:/VHDL/waitpast/dig_clk/sel6.vhdl 2007/03/16.17:01:34 I.24
FL E:/VHDL/waitpast/dig_clk/FPQ2MS.vhdl 2007/03/16.09:43:14 I.24
FL E:/VHDL/dig_clk/FEN_SOUND.vhdl 2007/03/16.10:02:50 I.24
FL E:/VHDL/dig_clk/xzq6.vhdl 2007/03/16.10:20:10 I.24
FL E:/VHDL/dig_clk/YMQ.vhdl 2007/03/16.09:50:00 I.24
FL e:/vhdl/dig_clk/FEN_SOUND.vhdl 2007/03/16.10:02:50 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl 2007/05/16.16:47:32 I.24
EN work/FPQ1S 1179308661           FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/FPQ1S/BEHAVIORAL 1179308662 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl \
      EN work/FPQ1S 1179308661
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl 2007/05/16.16:41:52 I.24
EN work/BSKZ 1179308657            FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/BSKZ/BEHAVIORAL 1179308658 FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl \
      EN work/BSKZ 1179308657
FL e:/vhdl/waitpast/dig_clk/ch_bcd_integer.vhdl 2007/04/18.10:49:18 I.24
FL D:/waitpast/dig_clk/FPQ1S.vhdl 2007/03/16.09:42:38 I.24
FL E:/VHDL/dig_clk/MIN.vhdl 2007/03/16.09:33:38 I.24
FL D:/waitpast/dig_clk/miao.vhdl 2007/03/20.11:13:58 I.24
FL e:/vhdl/dig_clk/bskz.vhdl 2007/03/16.10:11:30 I.24
FL E:/VHDL/waitpast/dig_clk/yimaqi.vhdl 2007/03/18.08:28:42 I.24
FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl 2007/05/16.17:19:34 I.24
EN work/s59 1179308667             FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl \
      PB ieee/std_logic_1164 1131108373 PB ieee/std_logic_arith 1131108375 \
      PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/s59/Behavioral 1179308668  FL F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl EN work/s59 1179308667
FL D:/waitpast/dig_clk/bskz.vhdl 2007/03/16.10:11:30 I.24