hdllib.ref

来自「数字钟的实现」· REF 代码 · 共 48 行

EN sec NULL E:/VHDL/waitpast/dig_clk/SECOND1.vhdl sub00/vhpl30 0
AR sel6 behavioral D:/waitpast/dig_clk/sel6.vhdl sub00/vhpl27 0
EN clock NULL E:/VHDL/waitpast/dig_clk/clock.vhf sub00/vhpl22 0
EN lcd NULL E:/VHDL/waitpast/dig_clk/lcd.vhdl sub00/vhpl40 0
EN sel NULL e:/vhdl/dig_clk/SEL.vhdl sub00/vhpl10 0
EN ymq NULL E:/VHDL/waitpast/dig_clk/YMQ.vhdl sub00/vhpl14 0
EN digclk NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf sub00/vhpl33 1179308671
AR yimaqi behavioral D:/waitpast/dig_clk/yimaqi.vhdl sub00/vhpl29 0
AR digclk behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf sub00/vhpl34 1179308672
AR fp4mhz behavioral E:/VHDL/waitpast/dig_clk/fpq4mhz.vhdl sub00/vhpl44 0
AR hour behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl sub00/vhpl05 1179308666
AR min behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl sub00/vhpl03 1179308664
AR ch_bcd_integer behavioral E:/VHDL/waitpast/dig_clk/ch_bcd_integer.vhdl sub00/vhpl38 0
EN second1 NULL E:/VHDL/waitpast/dig_clk/SECOND1.vhdl sub00/vhpl24 0
AR fpq2ms behavioral D:/waitpast/dig_clk/FPQ2MS.vhdl sub00/vhpl09 0
AR s59 behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl sub00/vhpl36 1179308668
AR sel behavioral e:/vhdl/dig_clk/SEL.vhdl sub00/vhpl11 0
EN miao NULL e:/vhdl/waitpast/dig_clk/miao.vhdl sub00/vhpl31 0
EN char_ram NULL E:/VHDL/waitpast/dig_clk/lcd.vhdl sub00/vhpl39 0
EN fpq2ms NULL D:/waitpast/dig_clk/FPQ2MS.vhdl sub00/vhpl08 0
AR miao behavioral e:/vhdl/waitpast/dig_clk/miao.vhdl sub00/vhpl32 0
EN fpq1s NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl sub00/vhpl06 1179308661
AR second1 behavioral E:/VHDL/waitpast/dig_clk/SECOND1.vhdl sub00/vhpl25 0
EN hour NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/HOUR.vhdl sub00/vhpl04 1179308665
EN fp4mhz NULL E:/VHDL/waitpast/dig_clk/fpq4mhz.vhdl sub00/vhpl43 0
AR lcd behavioral E:/VHDL/waitpast/dig_clk/lcd.vhdl sub00/vhpl42 0
EN min NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/MIN.vhdl sub00/vhpl02 1179308663
EN fpq_sound NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl sub00/vhpl16 1179308659
AR szq behavioral D:/waitpast/dig_clk/xzq6.vhdl sub00/vhpl21 0
AR fpq1s behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/FPQ1S.vhdl sub00/vhpl07 1179308662
AR clock behavioral E:/VHDL/waitpast/dig_clk/clock.vhf sub00/vhpl23 0
AR ymq behavioral E:/VHDL/waitpast/dig_clk/YMQ.vhdl sub00/vhpl15 0
AR char_ram fun E:/VHDL/waitpast/dig_clk/lcd.vhdl sub00/vhpl41 0
EN s59 NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/s59.vhdl sub00/vhpl35 1179308667
EN ch_bcd_integer NULL E:/VHDL/waitpast/dig_clk/ch_bcd_integer.vhdl sub00/vhpl37 0
EN lcd1602 NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd sub00/vhpl45 1179308669
AR lcd1602 behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd sub00/vhpl46 1179308670
EN s_6 NULL E:/VHDL/waitpast/dig_clk/S_6.vhdl sub00/vhpl12 0
EN sel6 NULL D:/waitpast/dig_clk/sel6.vhdl sub00/vhpl26 0
EN szq NULL D:/waitpast/dig_clk/xzq6.vhdl sub00/vhpl20 0
AR s_6 behavioral E:/VHDL/waitpast/dig_clk/S_6.vhdl sub00/vhpl13 0
AR fpq_sound behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl sub00/vhpl17 1179308660
AR second behavioral E:/VHDL/dig_clk/second.vhdl sub00/vhpl01 0
EN bskz NULL F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl sub00/vhpl18 1179308657
EN yimaqi NULL D:/waitpast/dig_clk/yimaqi.vhdl sub00/vhpl28 0
AR bskz behavioral F:/FPGA/VHDL/waitpast/dig_clk_lcd/bskz.vhdl sub00/vhpl19 1179308658
EN second NULL E:/VHDL/dig_clk/second.vhdl sub00/vhpl00 0