digclk.vhd

来自「数字钟的实现」· VHDL 代码 · 共 226 行

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-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 8.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : digclk.vhf
-- /___/   /\     Timestamp : 05/16/2007 17:22:26
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx\bin\nt\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.sch digclk.vhf
--Design Name: digclk
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity digclk is
   port ( clk      : in    std_logic; 
          clr      : in    std_logic; 
          rst      : in    std_logic; 
          shour    : in    std_logic; 
          smin     : in    std_logic; 
          lcd_data : out   std_logic_vector (7 downto 0); 
          lcd_en   : out   std_logic; 
          lcd_rs   : out   std_logic; 
          lcd_rw   : out   std_logic; 
          sound    : out   std_logic);
end digclk;

architecture BEHAVIORAL of digclk is
   attribute BOX_TYPE   : string ;
   signal XLXN_17  : std_logic;
   signal XLXN_30  : std_logic;
   signal XLXN_32  : std_logic;
   signal XLXN_33  : std_logic;
   signal XLXN_34  : std_logic;
   signal XLXN_37  : std_logic;
   signal XLXN_38  : std_logic;
   signal XLXN_39  : std_logic;
   signal XLXN_48  : std_logic_vector (3 downto 0);
   signal XLXN_49  : std_logic_vector (3 downto 0);
   signal XLXN_51  : std_logic_vector (3 downto 0);
   signal XLXN_52  : std_logic_vector (3 downto 0);
   signal XLXN_54  : std_logic_vector (3 downto 0);
   signal XLXN_61  : std_logic;
   signal XLXN_62  : std_logic;
   signal XLXN_63  : std_logic;
   signal XLXN_64  : std_logic;
   signal XLXN_73  : std_logic_vector (3 downto 0);
   component bskz
      port ( clk    : in    std_logic; 
             mshi   : in    std_logic_vector (3 downto 0); 
             mge    : in    std_logic_vector (3 downto 0); 
             sshi   : in    std_logic_vector (3 downto 0); 
             sge    : in    std_logic_vector (3 downto 0); 
             cp500  : out   std_logic; 
             cp1000 : out   std_logic);
   end component;
   
   component fpq_sound
      port ( CLK    : in    std_logic; 
             CP500  : out   std_logic; 
             CP1000 : out   std_logic);
   end component;
   
   component fpq1S
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component MIN
      port ( CLK    : in    std_logic; 
             EN     : in    std_logic; 
             COUT   : out   std_logic; 
             MINSHI : out   std_logic_vector (3 downto 0); 
             MINGE  : out   std_logic_vector (3 downto 0); 
             clr    : in    std_logic);
   end component;
   
   component HOUR
      port ( CLK     : in    std_logic; 
             EN      : in    std_logic; 
             HOURSHI : out   std_logic_vector (3 downto 0); 
             HOURGE  : out   std_logic_vector (3 downto 0); 
             clr     : in    std_logic);
   end component;
   
   component s59
      port ( CLK    : in    std_logic; 
             COUT   : out   std_logic; 
             SECSHI : out   std_logic_vector (3 downto 0); 
             SECGE  : out   std_logic_vector (3 downto 0); 
             clr    : in    std_logic);
   end component;
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component LCD1602
      port ( CLK      : in    std_logic; 
             Reset    : in    std_logic; 
             mg       : in    std_logic_vector (3 downto 0); 
             ms       : in    std_logic_vector (3 downto 0); 
             fg       : in    std_logic_vector (3 downto 0); 
             fs       : in    std_logic_vector (3 downto 0); 
             sg       : in    std_logic_vector (3 downto 0); 
             ss       : in    std_logic_vector (3 downto 0); 
             LCD_RS   : out   std_logic; 
             LCD_RW   : out   std_logic; 
             LCD_EN   : out   std_logic; 
             LCD_Data : out   std_logic_vector (7 downto 0));
   end component;
   
begin
   XLXI_1 : bskz
      port map (clk=>clk,
                mge(3 downto 0)=>XLXN_52(3 downto 0),
                mshi(3 downto 0)=>XLXN_51(3 downto 0),
                sge(3 downto 0)=>XLXN_54(3 downto 0),
                sshi(3 downto 0)=>XLXN_73(3 downto 0),
                cp500=>XLXN_33,
                cp1000=>XLXN_37);
   
   XLXI_2 : fpq_sound
      port map (CLK=>clk,
                CP500=>XLXN_32,
                CP1000=>XLXN_34);
   
   XLXI_3 : fpq1S
      port map (CLK=>clk,
                CP=>XLXN_17);
   
   XLXI_7 : MIN
      port map (CLK=>XLXN_17,
                clr=>clr,
                EN=>XLXN_30,
                COUT=>XLXN_63,
                MINGE(3 downto 0)=>XLXN_52(3 downto 0),
                MINSHI(3 downto 0)=>XLXN_51(3 downto 0));
   
   XLXI_8 : HOUR
      port map (CLK=>XLXN_17,
                clr=>clr,
                EN=>XLXN_64,
                HOURGE(3 downto 0)=>XLXN_49(3 downto 0),
                HOURSHI(3 downto 0)=>XLXN_48(3 downto 0));
   
   XLXI_19 : s59
      port map (CLK=>XLXN_17,
                clr=>clr,
                COUT=>XLXN_62,
                SECGE(3 downto 0)=>XLXN_54(3 downto 0),
                SECSHI(3 downto 0)=>XLXN_73(3 downto 0));
   
   XLXI_26 : OR2
      port map (I0=>XLXN_33,
                I1=>XLXN_32,
                O=>XLXN_39);
   
   XLXI_27 : OR2
      port map (I0=>XLXN_37,
                I1=>XLXN_34,
                O=>XLXN_38);
   
   XLXI_28 : AND2
      port map (I0=>XLXN_38,
                I1=>XLXN_39,
                O=>sound);
   
   XLXI_35 : AND2
      port map (I0=>shour,
                I1=>XLXN_61,
                O=>XLXN_64);
   
   XLXI_36 : AND2
      port map (I0=>smin,
                I1=>XLXN_62,
                O=>XLXN_30);
   
   XLXI_37 : OR2
      port map (I0=>XLXN_63,
                I1=>XLXN_62,
                O=>XLXN_61);
   
   XLXI_38 : LCD1602
      port map (CLK=>clk,
                fg(3 downto 0)=>XLXN_52(3 downto 0),
                fs(3 downto 0)=>XLXN_51(3 downto 0),
                mg(3 downto 0)=>XLXN_54(3 downto 0),
                ms(3 downto 0)=>XLXN_73(3 downto 0),
                Reset=>rst,
                sg(3 downto 0)=>XLXN_49(3 downto 0),
                ss(3 downto 0)=>XLXN_48(3 downto 0),
                LCD_Data(7 downto 0)=>lcd_data(7 downto 0),
                LCD_EN=>lcd_en,
                LCD_RS=>lcd_rs,
                LCD_RW=>lcd_rw);
   
end BEHAVIORAL;