ch_bcd_integer.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ch_bcd_integer is
  port(clk:in std_logic;
       h1,h2,f1,f2,m1,m2:in std_logic_vector(3 downto 0);
       d1,d2,d3,d4,d5,d6:out integer range 0 to 9);
end ch_bcd_integer;

architecture Behavioral of ch_bcd_integer is

begin
process(clk)
begin 
    if clk'event and clk='1' then
	    d1<=conv_integer(h2);
	    d2<=conv_integer(h1);
	    d3<=conv_integer(f2);
	    d4<=conv_integer(f1);
	    d5<=conv_integer(m2);
	    d6<=conv_integer(m1);
    end if;
end process;
end Behavioral;